Datasheet

ADS8363
ADS7263
ADS7223
www.ti.com SBAS523B –OCTOBER 2010–REVISED JANUARY 2011
Half-Clock Mode (default mode after power-up
DIGITAL
and reset)
This section reviews the timing and control of the
The ADS8363/7263/7223 power up in half-clock
serial interface.
mode, in which the ADC requires at least 20 CLOCKs
The ADS8363/7263/7223 offer a set of internal
for a complete conversion cycle, including the
registers (see the Register Map section for details),
acquisition phase. The conversion result can only be
which allows the control of several features and
read during the next conversion cycle. The first output
modes of the device, as Table 5 shows.
bit is available with the falling RD edge, while the
following output data bits are refreshed with the rising
Mode Selection Pin M0 and M1
edge of CLOCK.
The ADS8363/7263/7223 can be configured to four
Full-Clock Mode (allowing conversion and data
different operating modes by using mode pins M0
readout within 1µs, supported in dual output
and M1, as shown in Table 4.
modes)
Table 4. M0/M1 Truth Table
The full-clock mode allows converting data and
reading the result within 1µs. The entire cycle
CHANNEL
requires 40 CLOCKs. The first output bit is available
M0 M1 SELECTION SDOx USED
with the falling RD edge while the following output
0 0 Manual (through SDI) SDOA and SDOB
data bits are refreshed with the falling edge of the
0 1 Manual (through SDI) SDOA only
CLOCK in this mode.
1 0 Automatic SDOA and SDOB
The full-clock mode can only be used with analog
1 1 Automatic SDOA only
power supply AVDD in the range of 4.5V to 5.5V and
digital supply DVDD in the range of 2.3V to 3.6V. The
The M0 pin sets either manual or automatic channel
internal FIFO is disabled in full-clock mode.
selection. In Manual mode, CONFIG register bits
C[1:0] are used to select between channels CHx0
2-Bit Counter
and CHx1. In Automatic mode, CONFIG register bits
C[1:0] are ignored and channel selection is controlled
These devices offers a selectable 2-bit counter
by the device after each conversion. The automatic
(activated using the CE bit in the CONFIG register)
channel selection is only performed on
that is a useful feature in safety applications. The
fully-differential inputs in this case; for
counter value automatically increments whenever a
pseudo-differential inputs, the internal sequencer
new conversion result is stored in the output register,
controls the input multiplexer.
indicating a new value. The counter default value
after power-up is '01' (followed by '10', '11', '00', '01',
The M1 pin selects between serial data being
and so on), as shown in Figure 31. Because the
transmitted simultaneously on both SDOA and SDOB
counter value increments only when a new
outputs for each channel, respectively, or using only
conversion results are transferred to the output
the SDOA output for transmitting data from both
register, this counter is used to verify that the ADC
channels (see Figure 34 through Figure 39 and the
has performed a conversion and the data read is the
associated text for more information).
result of this new conversion (not a old result read
Additionally, the SDI pin is used for controlling device
multiple times).
functionality through the internal register; see the
Register Map section for details.
Table 5. Supported Operating Modes
INPUT SIGNAL TYPE MANUAL CHANNEL SELECTION AUTOMATIC CHANNEL SELECTION
Operating modes: III, IV and special mode IV
Operating modes: I, II, and special mode II
Fully-differential Channel information selectable through CID bit
Channel information selectable through CID bit
(PDE bit = '0') FIFO: available in mode III and special mode IV;
FIFO: not available
when used, a single read pulse allows reading of all data
Operating modes: III and special mode IV
Operating modes: I, II and special mode II Channel information not available (CID bit forced to '1')
Pseudo-differential
Channel information selectable through CID bit FIFO: available in mode III and special mode IV;
(PDE bit = '1')
FIFO: not available when used, a single read pulse allows reading of all data
Pseudo-differential sequencer is enabled
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