Datasheet

ADS6445, ADS6444
ADS6443, ADS6442
SLAS531B –MAY 2007–REVISED DECEMBER 2009 www.ti.com
For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode
noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Bandpass
filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a
non-50% duty cycle clock input.
CLOCK BUFFER GAIN
When using a sinusoidal clock input, the noise contributed by clock jitter improves as the clock amplitude is
increased. Hence, it is recommended to use large clock amplitude. As shown by Figure 18, use clock amplitude
greater than 1V
PP
to avoid performance degradation.
In addition, the clock buffer has programmable gain to amplify the input clock to support very low clock
amplitude. The gain can be set by programming the register bits <CLKIN GAIN> (refer to Table 14) and
increases monotonically from Gain 0 to Gain 5 settings. Table 22 lists the minimum clock amplitude supported for
each gain setting.
Table 22. Minimum Clock Amplitude across gains
MINIMUM CLOCK AMPLITUDE SUPPORTED
CLOCK BUFFER GAIN
mV
PP
differential
Gain 0 (minimum gain) 800
Gain 1 (default gain) 400
Gain 2 300
Gain 3 200
Gain 4 150
Gain 5 (highest gain) 100
POWER DOWN MODES
The ADS644X has three power down modes – global power down, channel standby and input clock stop.
Global Power Down
This is a global power down mode in which almost the entire chip is powered down, including the four ADCs,
internal references, PLL and LVDS buffers. As a result, the total power dissipation falls to about 77 mW typical
(with input clock running). This mode can be initiated by setting the register bit <PDN GLOBAL> (refer to
Table 13). The output data and clock buffers are in high impedance state.
The wake-up time from this mode to data becoming valid in normal mode is 100 μs.
Channel Standby
In this mode, only the ADC of each channel is powered down and this helps to get very fast wake-up times. Each
of the four ADCs can be powered down independently using the register bits <PDN CH> (refer to Table 13). The
output LVDS buffers remain powered up.
The wake-up time from this mode to data becoming valid in normal mode is 200 clock cycles.
Input Clock Stop
The converter enters this mode:
• If the input clock frequency falls below 1 MSPS or
• If the input clock amplitude is less than 400 mV
PP
, differential with default clock buffer gain setting) at any
sampling frequency.
All ADCs and LVDS buffers are powered down and the power dissipation is about 235 mW. The wake-up time
from this mode to data becoming valid in normal mode is 100 μs.
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