Datasheet

S0167-05
CLKP
CLKM
DifferentialSine-Wave
orPECL orLVDSClockInput
ADS6xxx
0.1 Fm
0.1 Fm
V
CC
V
CC
REF_IN
VCXO_INM
CP_OUT
CTRL
OUTP
OUTM
Y0B
Y0
ADS6xxx
CLKM
CLKP
VCXO
CDCM7005
VCXO_INP
Reference Clock
S0238-02
S0168-07
CLKP
CLKM
CMOSClockInput
ADS6xxx
0.1 Fm
0.1 Fm
ADS6445, ADS6444
ADS6443, ADS6442
www.ti.com SLAS531B –MAY 2007–REVISED DECEMBER 2009
Figure 90. Differential Clock Driving Circuit
Figure 91 shows a typical scheme using PECL clock drive from a CDCM7005 clock driver. SNR performance
with this scheme is comparable with that of a low jitter sine wave clock source.
Figure 91. PECL Clock Drive Using CDCM7005
Single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM (pin) connected to ground with a
0.1-μF capacitor, as shown in Figure 92.
Figure 92. Single-Ended Clock Driving Circuit
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Product Folder Link(s): ADS6445, ADS6444 ADS6443, ADS6442