Datasheet

S0166-04

CLKP

VCM

5kW

CLKM

VCM

ADS6xxx

ADS6445, ADS6444

ADS6443, ADS6442

SLAS531B –MAY 2007–REVISED DECEMBER 2009

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So, the fine gain can be used to trade-off between SFDR and SNR. The coarse gain makes it possible to get

best SFDR but without losing SNR significantly. At high input frequencies, the gains are especially useful as the

SFDR improvement is significant with marginal degradation in SINAD.

The gains can be programmed using the register bits <COARSE GAIN> (refer to Table 18) and <FINE GAIN>

(refer to Table 17). Note that the default gain after reset is 0 dB.

Table 21. Full-Scale Range Across Gains

GAIN, dB TYPE FULL-SCALE, V

0 Default (after reset) 2

3.5 Coarse setting (fixed) 1.34

1 1.78

2 1.59

3 1.42

Fine setting (programmable)

4 1.26

5 1.12

6 1.00

CLOCK INPUT

The ADS644X clock inputs can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS),

with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to

VCM using internal 5-kΩ resistors as shown in Figure 89. This allows using transformer-coupled drive circuits for

sine wave clock or ac-coupling for LVPECL, LVDS clock sources (see Figure 90 and Figure 92).

Figure 89. Internal Clock Buffer

Product Folder Link(s): ADS6445, ADS6444 ADS6443, ADS6442