Datasheet

ADS6445, ADS6444
ADS6443, ADS6442
SLAS531B –MAY 2007–REVISED DECEMBER 2009 www.ti.com
PIN ASSIGNMENTS (2-WIRE INTERFACE) (continued)
PINS
NO. OF
I/O DESCRIPTION
PINS
NAME NO.
Differential input signal pair, channel A. If unused, the pins should be tied to VCM. Do
INA_P, INA_M 12,11 I 2
not float.
Differential input signal pair, channel B. If unused, the pins should be tied to VCM. Do
INB_P, INB_M 15,14 I 2
not float.
Differential input signal pair, channel C If unused, the pins should be tied to VCM. Do
INC_P, INC_M 34,35 I 2
not float.
Differential input signal pair, channel D. If unused, the pins should be tied to VCM. Do
IND_P, IND_M 37,38 I 2
not float.
CAP 5 1 Connect 2-nF capacitor from pin to ground
This pin functions as serial interface clock input when RESET is low.
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes
SCLK 44 I 1
(along with SDATA). Refer to Table 5 for description.
This pin has an internal pull-down resistor.
This pin functions as serial interface data input when RESET is low.
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes
SDATA 43 I 1
(along with SCLK). Refer to Table 5 for description.
This pin has an internal pull-down resistor.
This pin functions as serial interface enable input when RESET is low.
When RESET is high, it controls coarse gain and internal/external reference modes.
SEN 42 I 1
Refer to Table 6 for description.
This pin has an internal pull-up resistor.
Serial interface reset input.
When using the serial interface mode, the user MUST initialize internal registers
through hardware RESET by applying a high-going pulse on this pin or by using
RESET 6 I 1 software reset option. Refer to the Serial Interface section. In parallel interface mode,
tie RESET permanently high. (SCLK, SDATA and SEN function as parallel control
pins in this mode).
The pin has an internal pull-down resistor to ground.
PDN 41 I 1 Global power down control pin.
Parallel input pin. It controls 1-wire or 2-wire interface and DDR or SDR bit clock
CFG1 30 I 1 selection. Refer to Table 8 for description.
Tie to AVDD for 2-wire interface with DDR bit clock.
Parallel input pin. It controls 14x or 16x serialization and SDR bit clock capture edge.
CFG2 29 I 1 Refer to Table 9 for description.
For 14x serialization with DDR bit clock, tie to ground or AVDD.
CFG3 28 I 1 RESERVED pin - Tie to ground.
Parallel input pin. It controls data format and MSB or LSB first modes. Refer to
CFG4 21 I 1
Table 11 for description.
Internal reference mode – common-mode voltage output
VCM 22 I/O 1 External reference mode – reference input. The voltage forced on this pin sets the
internal reference.
OUTPUT PINS
DA0_P,DA0_M 3,4 O 2 Channel A differential LVDS data output pair, wire 0
DA1_P,DA1_M 1,2 O 2 Channel A differential LVDS data output pair, wire 1
DB0_P,DB0_M 62,63 O 2 Channel B differential LVDS data output pair, wire 0
DB1_P,DB1_M 60,61 O 2 Channel B differential LVDS data output pair, wire 1
DC0_P,DC0_M 52,53 O 2 Channel C differential LVDS data output pair, wire 0
DC1_P,DC1_M 50,51 O 2 Channel C differential LVDS data output pair, wire 1
DD0_P,DD0_M 47,48 O 2 Channel D differential LVDS data output pair, wire 0
DD1_P,DD1_M 45,46 O 2 Channel D differential LVDS data output pair, wire 1
DCLKP,DCLKM 57,58 O 2 Differential bit clock output pair
FCLKP,FCLKM 55,56 O 2 Differential frame clock output pair
NC 20 1 Do Not Connect
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