Datasheet

ADS6445, ADS6444
ADS6443, ADS6442
SLAS531B –MAY 2007–REVISED DECEMBER 2009 www.ti.com
Table 16. Serial Register D
REGISTER
BITS
(1)
ADDRESS
A4 - A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
<CUSTOM A>
0B
CUSTOM PATTERN (LOWER 11 BITS)
(1) After a hardware or software reset, all register bits are cleared to 0.
D10 - D0 <CUSTOM A> Lower 11 bits of custom pattern <D10>…<D0>
Table 17. Serial Register E
REGISTER
BITS
(1)
ADDRESS
A4 - A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
<FINE GAIN> <CUSTOM B>
0C 0 0 0 0 0
FINE GAIN CONTROL (1 dB to 6 dB) CUSTOM PATTERN (UPPER 3 BITS)
(1) After a hardware or software reset, all register bits are cleared to 0.
D4 - D0 <CUSTOM B> Upper 3 bits of custom pattern <D13>…<D11>
D10-D8 <FINE GAIN> Fine gain control
000 0 dB Gain (full-scale range = 2.00 V
PP
)
001 1 dB Gain (full-scale range = 1.78 V
PP
)
010 2 dB Gain (full-scale range = 1.59 V
PP
)
011 3 dB Gain (full-scale range = 1.42 V
PP
)
100 4 dB Gain (full-scale range = 1.26 V
PP
)
101 5 dB Gain (full-scale range = 1.12 V
PP
)
110 6 dB Gain (full-scale range = 1.00 V
PP
)
Table 18. Serial Register F
REGISTER
BITS
(1)
ADDRESS
A4 - A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
<COARSE FALLING OR
<OVRD> BYTE-WISE GAIN> RISING BIT 14-BIT OR DDR OR 1-WIRE OR
MSB OR
0D OVER-RIDE 0 0 OR COURSE CLOCK 0 16-BIT SDR BIT 2-WIRE
LSB FIRST
BITE BIT-WISE GAIN CAPTURE SERIALIZE CLOCK INTERFACE
ENABLE EDGE
(1) After a hardware or software reset, all register bits are cleared to 0.
D0 Interface selection
0 1 Wire interface
1 2 Wire interface
D1 Bit clock selection (only in 2-wire interface)
0 DDR Bit clock
1 SDR Bit clock
D2 Serialization factor selection
0 14X Serialization
1 16X Serialization
D4 Bit clock capture edge (only when SDR bit clock is selected, D1 = 1)
0 Capture data with falling edge of bit clock
1 Capture data with rising edge of bit clock
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