Datasheet

ADS6445, ADS6444
ADS6443, ADS6442
SLAS531B –MAY 2007–REVISED DECEMBER 2009 www.ti.com
DESCRIPTION OF SERIAL REGISTERS
Table 13. Serial Register A
REGISTER
BITS
(1)
ADDRESS
A4 - A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
<REF> <PDN>
<PDN CHD> <PDN CHC> <PDN CHB> <PDN CHA>
<RST> INTERNAL GLOBAL
00 0 0 0 0 POWER POWER POWER POWER
S/W RESET OR POWER
DOWN CH D DOWN CHC DOWN CH B DOWN CH A
EXTERNAL DOWN
(1) After a hardware or software reset, all register bits are cleared to 0.
D0 - D4 Power down modes
D0 <PDN GLOBAL>
0 Normal operation
1 Global power down, including all channels ADCs, internal references, internal PLL and output
buffers
D1 <PDN CHA>
0 CH A Powered up
1 CH A ADC Powered down
D2 <PDN CHB>
0 CH B Powered up
1 CH B ADC Powered down
D3 <PDN CHC>
0 CH C Powered up
1 CH C ADC Powered down
D4 <PDN CHD>
0 CH D Powered up
1 CH D ADC Powered down
D5 <REF> Reference
0 Internal reference enabled
1 External reference enabled
D10 <RST>
1 Software reset applied – resets all internal registers and self-clears to 0
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