Datasheet

(3/6)LVDD
(3/6)LVDD
ToCFGxPins
3R
LVDD
LVDDGND
GND
R
2R
(5/6)LVDD
(5/6)LVDD
(3/8)LVDD
(3/8)LVDD
ToSENPin
3R
LVDD
LVDDGND
GND
3R
2R
(5/8)LVDD
(5/8)LVDD
ADS6445, ADS6444
ADS6443, ADS6442
SLAS531B –MAY 2007–REVISED DECEMBER 2009 www.ti.com
Table 4. Priority Between Parallel Pins and Serial Registers
PIN FUNCTIONS SUPPORTED PRIORITY
As described in Table 8 to Register bits can control the modes only if the register bit <OVRD> is high. If <OVRD> bit
CFG1 to CFG4
Table 11 is low, then the control voltage on these parallel pins determines the function.
Register bit <PDN GLOBAL> controls global power down only if PDN pin is low. If PDN is
PDN Global Power Down
high, device is in global power down.
Coarse gain is controlled by register bit <COARSE GAIN> only if the <OVRD> bit is high.
Else, device has 0 dB coarse gain.
SEN Serial Interface Enable
Internal/External Reference setting is determined by register bit <REF>.
Register bits <PATTERNS> control the sync and deskew output patterns.
Serial Interface Clock and
SCLK, SDATA
Serial Interface Data pins
Power down is determined by bit <PDN GLOBAL>
Figure 3. Simple Scheme to Configure Parallel Pins
14 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS6445, ADS6444 ADS6443, ADS6442