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BOARD DESIGN CONSIDERATIONS
Grounding
Supply Decoupling
Exposed Thermal Pad
ADS6424
ADS6423
ADS6422
SLAS532A – MAY 2007 – REVISED JUNE 2007
Table 30. Timings for 2-Wire Interface, SDR Bit Clock
DATA SETUP TIME, t
su
DATA HOLD TIME, t
h
t
delay
SAMPLING
ns ns ns
SERIALIZATION FREQUENCY
MSPS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
65 1.0 1.2 1.1 1.3 F
s
≥ 40 MSPS
40 1.8 2.0 1.9 2.1 3.4 4.4 5.4
12 ×
20 3.9 4.1 3.8 4.1 F
s
< 40 MSPS
10 8.2 8.4 7.8 8.2 3.7 5.2 6.7
65 0.8 1.0 1.0 1.2 F
s
≥ 40 MSPS
40 1.5 1.7 1.6 1.8 3.4 4.4 5.4
14 ×
20 3.4 3.6 3.3 3.5 F
s
< 40 MSPS
10 6.9 7.2 6.6 6.9 3.7 5.2 6.7
Table 31. Output Jitter (applies to all interface options)
BIT CLOCK JITTER, CYCLE-CYCLE FRAME CLOCK JITTER, CYCLE-CYCLE
SAMPLING FREQUENCY
ps, peak-peak ps, peak-peak
MSPS
MIN TYP MAX MIN TYP MAX
≥ 65 350 75
A single ground plane is sufficient to give optimum performance, provided the analog, digital and clock sections
of the board are cleanly partitioned. Refer to the EVM User Guide (SLAU196 ) for more layout details.
As the ADS644X already includes internal decoupling, minimal external decoupling can be used without loss in
performance. Note that the decoupling capacitors can help to filter external power supply noise, so the optimum
number of decoupling capacitors would depend on actual application.
It is recommended to use separate supplies for the analog and digital supply pins to isolate digital switching
noise from sensitive analog circuitry. In case only a single 3.3-V supply is available, it should be routed first to
AVDD. It can then be tapped and isolated with a ferrite bead (or inductor) with decoupling capacitor, before being
routed to LVDD.
It is necessary to solder the exposed pad at the bottom of the package to a ground plane for best thermal
performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122 A) and
QFN/SON PCB Attachment (SLUA271 A).
Copyright © 2007, Texas Instruments Incorporated 59
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