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OUTPUT TIMINGS AT LOWER SAMPLING FREQUENCIES
ADS6424
ADS6423
ADS6422
SLAS532A – MAY 2007 – REVISED JUNE 2007
Setup, hold and other timing parameters are specified across sampling frequencies and for each type of output
interface in the following tables.
Table 28 to Table 31 : Typical values are at 25 ° C, min and max values are across the full temperature range T
MIN
= – 40 ° C to T
MAX
= 85 ° C, AVDD = LVDD = 3.3 V, C
L
= 5 pF , I
O
= 3.5 mA, R
L
= 100 Ω , no internal termination,
unless otherwise noted.
Timing parameters are ensured by design and characterization and not tested in production.
Ts = 1/ Sampling frequency = 1/Fs
Table 27. Clock Propagation Delay and Serializer Latency for different interface options
SERIALIZER LATENCY
(1)
INTERFACE SERIALIZATION CLOCK PROPAGATION DELAY, t
pd_clk
clock cycles
12X t
pd_clk
= 0.5xT
s
+ t
delay
1-Wire with DDR bit clock 0
14X t
pd_clk
= 0.428xT
s
+ t
delay
2-Wire with DDR bit clock t
pd_clk
= t
delay
1
12X
2-Wire with SDR bit clock t
pd_clk
= 0.5xT
s
+ t
delay
0
2
(when t
pd_clk
≥ T
s
)
2-Wire with DDR bit clock t
pd_clk
= 0.857xT
s
+ t
delay
14X 1
(when t
pd_clk
< T
s
)
2-Wire with SDR bit clock t
pd_clk
= 0.428xT
s
+ t
delay
0
(1) Note that the total latency = ADC latency + serializer latency. The ADC latency is 12 clocks.
Table 28. Timings for 1-Wire Interface
DATA SETUP TIME, t
su
DATA HOLD TIME, t
h
t
delay
SAMPLING
ns ns ns
SERIALIZATION FREQUENCY
MSPS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
65 0.4 0.6 0.5 0.7 F
s
≥ 40 MSPS
40 0.8 1.0 0.9 1.1 3 4 5
12 ×
20 1.6 2.0 1.8 2.2 F
s
< 40 MSPS
10 3.5 4.0 3.5 4.2 3 4.5 6
65 0.3 0.5 0.4 0.6 F
s
≥ 40 MSPS
40 0.65 0.85 0.7 0.9 3 4 5
14 ×
20 1.3 1.65 1.6 1.9 F
s
< 40 MSPS
10 3.2 3.5 3.2 3.6 3 4.5 6
Table 29. Timings for 2-Wire Interface, DDR Bit Clock
DATA SETUP TIME, t
su
DATA HOLD TIME, t
h
t
delay
SAMPLING
ns ns ns
SERIALIZATION FREQUENCY
MSPS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
105 0.55 0.75 0.6 0.8 F
s
≥ 45 MSPS
92 0.65 0.85 0.7 0.9
3.4 4.4 5.4
12 × 80 0.8 1.0 0.8 1.05
65 0.9 1.2 1.0 1.3 F
s
< 45 MSPS
40 1.7 2.0 1.1 2.1 3.7 5.2 6.7
105 0.45 0.65 0.5 0.7 F
s
≥ 45 MSPS
92 0.55 0.75 0.6 0.8
3 4 5
14 × 80 0.65 0.85 0.7 0.9
65 0.8 1.1 0.8 1.1 F
s
< 45 MSPS
40 1.4 1.7 1.5 1.9 3 4.5 6
58 Copyright © 2007, Texas Instruments Incorporated
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