Datasheet

www.ti.com

2-WIRE INTERFACE - 14 × SERIALIZATION

ADS6424

ADS6423

ADS6422

SLAS532A – MAY 2007 – REVISED JUNE 2007

In 14 × serialization, two zero bits are padded to the 14-bit ADC data on the MSB side and the combined 14-bit

data is serialized and output over two LVDS pairs. A frame clock at 1 × sample frequency is also available with an

SDR bit clock. With DDR bit clock option, the frame clock frequency is 0.5 × sample frequency. The output data

rate will be 7 × sample frequency as 7 data bits are output every clock cycle on each wire. Each ADC sample is

sent over the 2 wires as byte-wise or bit-wise or word-wise.

Using the 14 × serialization makes it possible to upgrade to a 14-bit ADC in the 64xx family in the future

seamlessly, without requiring any modification to the receiver capture logic design.

Submit Documentation Feedback

Product Folder Link(s): ADS6424 ADS6423 ADS6422