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0
(D0)
D13
(D2)
D6
(D7)
D10
(D3)
D3
(D10)
D7
(D6)
D0
(0)
0
(D1)
0
(D1)
D5
(D8)
D9
(D4)
D2
(D11)
D11
(D2)
D4
(D9)
D8
(D5)
D1
(0)
0
(D0)
DataBitinLSBFirstMode
DataBitinMSBFirstMode
(1)
In14-Bitserialization,twozerobitsarepaddedtothe12-bit ADCdataontheMSBside.
OutputData
DA,DB,DC,DD
DataRate=14 Fs´
14-BitSerialization
(1)
InputClock,
CLK
Freq=Fs
FrameClock,
FCLK
Freq=1 Fs´
BitClock,
DCLK
Freq=7 Fs´
T0225-01
D11
(D0)
D11
(D0)
D5
(D6)
D8
(D3)
D2
(D9)
D10
(D1)
D10
(D1)
D4
(D7)
D7
(D4)
D1
(D10)
D9
(D2)
D3
(D8)
D6
(D5)
D0
(D11)
OutputData
DA,DB,DC,DD
DataRate=12 Fs´
12-BitSerialization
BitClock,
DCLK
Freq=6 Fs´
SampleN SampleN+1
2-WIRE INTERFACE - 12 × SERIALIZATION WITH DDR/SDR BIT CLOCK
ADS6424
ADS6423
ADS6422
SLAS532A – MAY 2007 – REVISED JUNE 2007
Figure 75. 1-Wire Interface
The 2-wire interface is recommended for sampling frequencies above 65 MSPS. The device outputs the data of
each ADC serially on two LVDS pairs (2-wire). The data rate is 6 × sample frequency since 6 bits are sent on
each wire every clock cycle. The data is available along with DDR bit clock or optionally with SDR bit clock. Each
ADC sample is sent over the 2 wires as byte-wise or bit-wise or word-wise.
50 Copyright © 2007, Texas Instruments Incorporated
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