Datasheet
www.ti.com
ELECTRICAL CHARACTERISTICS
ADS6424
ADS6423
ADS6422
SLAS532A – MAY 2007 – REVISED JUNE 2007
Typical values are at 25 ° C, min and max values are across the full temperature range T
MIN
= – 40 ° C to T
MAX
= 85 ° C, AVDD =
LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, – 1dBFS differential analog input, internal reference
mode (unless otherwise noted).
ADS6424 ADS6423 ADS6422
F
s
= 105 MSPS F
s
= 80 MSPS F
s
= 65 MSPS
PARAMETER UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
RESOLUTION 12 12 12 Bits
ANALOG INPUT
Differential input voltage 2.0 2.0 2.0 V
PP
range
Differential input 7 7 7 pF
capacitance
Analog input bandwidth 500 500 500 MHz
Analog input common 130 100 81 μ A
mode current (per input pin
of each ADC)
REFERENCE VOLTAGES
VREFB Internal reference bottom 1.0 1.0 1.0 V
voltage
VREFT Internal reference top 2.0 2.0 2.0 V
voltage
Δ V
REF
Internal reference error, -15 ± 2 15 -15 ± 2 15 -15 ± 2 15 mV
(VREFT – VREFB)
VCM Common mode output 1.5 1.5 1.5 V
voltage
VCM output current ± 4 ± 4 ± 4 mA
capability
DC ACCURACY
No missing codes Specified Specified Specified
E
O
Offset error, across devices – 15 ± 2 15 – 15 ± 2 15 – 15 ± 2 15 mV
and across channels within
a device
Offset error temperature 0.05 0.05 0.05 mV/ ° C
coefficient, across devices
and across channels within
a device
There are two sources of gain error - internal reference inaccuracy and channel gain error
E
GREF
Gain error due to internal -0.75 ± 0.1 0.75 -0.75 ± 0.1 0.75 -0.75 ± 0.1 0.75 % FS
reference inaccuracy alone,
( Δ V
REF
/2.0) %
Reference gain error 0.0125 0.0125 0.0125 Δ %/ ° C
temperature coefficient
E
GCHAN
Gain error of channel – 1 ± 0.3 1 – 1 ± 0.3 1 – 1 ± 0.3 1 % FS
alone, across devices and
across channels within a
device
(1)
Channel gain error 0.005 0.005 0.005 Δ %/ ° C
temperature coefficient,
across devices and across
channels within a device
DNL Differential nonlinearity – 0.9 ± 0.5 2.0 – 0.9 ± 0.4 1.8 – 0.9 ± 0.4 1.8 LSB
INL Integral nonlinearity – 2.2 ± 1.25 2.2 – 2.0 ± 1.25 2.0 – 2.0 ± 1.0 2.0 LSB
PSRR DC power supply rejection 0.5 0.5 0.5 mV/V
ratio
(1) This is specified by design and characterization; it is not tested in production.
Copyright © 2007, Texas Instruments Incorporated 5
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