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DIGITAL OUTPUT INTERFACE

1-WIRE INTERFACE - 12 × AND 14 × SERIALIZATION WITH DDR BIT CLOCK

ADS6424

ADS6423

ADS6422

SLAS532A – MAY 2007 – REVISED JUNE 2007

The ADS642X offers several flexible output options making it easy to interface to an ASIC or an FPGA. Each of

these options can be easily programmed using either parallel pins or the serial interface.

The output interface options are:

• 1-Wire, 1 × frame clock, 12 × and 14 × serialization with DDR bit clock

• 2-Wire, 1 × frame clock, 12 × serialization, with DDR and SDR bit clock, byte wise/bit wise/word wise

• 2-Wire, 1 × frame clock, 14 × serialization, with SDR bit clock, byte wise/bit wise/word wise

• 2-Wire, (0.5 x) frame clock, 14 × serialization, with DDR bit clock, byte wise/bit wise/word wise.

The maximum sampling frequency, bit clock frequency and output data rate will vary depending on the interface

options selected (refer to Table 12 ).

Table 24. Maximum Recommended Sampling Frequency for Different Output Interface Options

MAXIMUM

RECOMMENDED BIT CLOCK

FRAME CLOCK SERIAL DATA RATE,

INTERFACE OPTIONS SAMPLING FREQUENCY,

FREQUENCY, MHZ Mbps

FREQUENCY, MHZ

MSPS

12 × Serialization 65 390 65 780

DDR Bit

1-Wire

clock

14 × Serialization 65 455 65 910

12 × Serialization 125 375 125 750

DDR Bit

2-Wire

clock

14 × Serialization 125 437.5 62.5 875

12 × Serialization 65 390 65 390

SDR Bit

2-Wire

clock

14 × Serialization 65 455 65 455

Each interface option is described in detail below.

Here the device outputs the data of each ADC serially on a single LVDS pair (1-wire). The data is available at the

rising and falling edges of the bit clock (DDR bit clock). The ADC outputs a new word at the rising edge of every

frame clock, starting with the MSB. Optionally, it can also be programmed to output the LSB first. The data rate is

12 × sample frequency (12 × serialization) and 14 × sample frequency (14 × serialization).

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