Datasheet

www.ti.com

REF_IN

VCXO_INM

CP_OUT

CTRL

OUTP

OUTM

Y0B

ADS6xxx

CLKM

CLKP

VCXO

CDCM7005

VCXO_INP

Reference Clock

S0238-02

S0168-07

CLKP

CLKM

CMOSClockInput

ADS6xxx

0.1 Fm

CLOCK BUFFER GAIN

ADS6424

ADS6423

ADS6422

SLAS532A – MAY 2007 – REVISED JUNE 2007

Figure 73. PECL Clock Drive Using CDCM7005

Single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM (pin) connected to ground with a

0.1- μ F capacitor, as shown in Figure 74 .

Figure 74. Single-Ended Clock Driving Circuit

For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode

noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Bandpass

filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a

non-50% duty cycle clock input.

When using a sinusoidal clock input, the noise contributed by clock jitter improves as the clock amplitude is

increased. Hence, it is recommended to use large clock amplitude. Use clock amplitude greater than 1 V

avoid performance degradation.

In addition, the clock buffer has programmable gain to amplify the input clock to support very low clock

amplitude. The gain can be set by programming the register bits <CLKIN GAIN> (refer to Table 14 ) and

increases monotonically from Gain 0 to Gain 4 settings. Table 22 lists the minimum clock amplitude supported for

each gain setting.

Submit Documentation Feedback