Datasheet

www.ti.com
S0166-04
CLKP
VCM
5kW
5kW
CLKM
VCM
ADS6xxx
S0167-05
CLKP
CLKM
DifferentialSine-Wave
orPECL orLVDSClockInput
ADS6xxx
0.1 Fm
0.1 Fm
ADS6424
ADS6423
ADS6422
SLAS532A – MAY 2007 – REVISED JUNE 2007
Figure 71. Internal Clock Buffer
Figure 72. Differential Clock Driving Circuit
Figure 73 shows a typical scheme using PECL clock drive from a CDCM7005 clock driver. SNR performance
with this scheme is comparable with that of a low jitter sine wave clock source.
46 Copyright © 2007, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6424 ADS6423 ADS6422