Datasheet

www.ti.com

COARSE GAIN AND PROGRAMMABLE FINE GAIN

CLOCK INPUT

ADS6424

ADS6423

ADS6422

SLAS532A – MAY 2007 – REVISED JUNE 2007

APPLICATION INFORMATION (continued)

ADS642X includes gain settings that can be used to get improved SFDR performance (compared to 0 dB gain

mode). The gain settings are 3.5 dB coarse gain and programmable fine gain from 0 dB to 6 dB. For each gain

setting, the analog input full-scale range scales proportionally, as listed in Table 21 .

The coarse gain is a fixed setting of 3.5 dB and is designed to improve SFDR with little degradation in SNR. The

fine gain is programmable in 1 dB steps from 0 to 6 dB. With fine gain also, SFDR improvement is achieved, but

at the expense of SNR (there is about 1dB SNR degradation for every 1dB of fine gain).

So, the fine gain can be used to trade-off between SFDR and SNR. The coarse gain makes it possible to get

best SFDR but without losing SNR significantly. At high input frequencies, the gains are especially useful as the

SFDR improvement is significant with marginal degradation in SINAD.

The gains can be programmed using the register bits <COARSE GAIN> (refer to Table 18 ) and <FINE GAIN>

(refer to Table 17 ). Note that the default gain after reset is 0 dB.

Table 21. Full-Scale Range Across Gains

GAIN, dB TYPE FULL-SCALE, V

0 Default (after reset) 2

3.5 Coarse setting (fixed) 1.34

1 1.78

2 1.59

3 1.42

Fine setting (programmable)

4 1.26

5 1.12

6 1.00

The ADS642X clock inputs can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS),

with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to

VCM using internal 5-k Ω resistors as shown in Figure 71 . This allows using transformer-coupled drive circuits for

sine wave clock or ac-coupling for LVPECL, LVDS clock sources (see Figure 72 and Figure 74 ).

Submit Documentation Feedback