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SNR − dBFS
70
71
72
73
74
75
76
77
78
80
82
84
86
88
90
92
94
96
0.5 1.0 1.5 2.0 2.5
SFDR − dBc
Input Clock Amplitude − V
PP
G049
SNR
SFDR
f
IN
= 50.1 MHz
SNR − dBFS
69
70
71
72
73
74
Input Clock Duty Cycle − %
73
75
77
79
81
83
35 40 45 50 55 60 65
SFDR − dBc
G050
SNR
SFDR
f
IN
= 20.1 MHz
f
S
− Sampling Frequency − MSPS
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0 10 20 30 40 50 60
P
D
− Power Dissipation − W
G069
LVDD
AVDD
Output Code
0
5
10
15
20
25
30
35
40
2045 2046 2047 2048 2049 2050 2051 2052 2053 2054
Occurence − %
G052
RMS (LSB) = 0.407
f − Frequency − MHz
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 50 100 150 200 250 300
CMRR − Common-Mode Rejection Ratio − dBc
G018
SNR − dBFS
64
66
68
70
72
74
V
VCM
− VCM Voltage − V
86
88
90
92
94
96
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70
f
IN
= 50.1 MHz
External Reference Mode
SFDR − dBc
G053
SNR
SFDR
ADS6424
ADS6423
ADS6422
SLAS532A – MAY 2007 – REVISED JUNE 2007
ADS6422 (F
srated
= 65 MSPS) (continued)
PERFORMANCE vs CLOCK AMPLITUDE PERFORMANCE vs CLOCK DUTY CYCLE
Figure 54. Figure 55.
OUTPUT NOISE HISTOGRAM WITH
POWER DISSIPATION vs SAMPLING FREQUENCY INPUTS TIED TO COMMON-MODE
Figure 56. Figure 57.
PERFORMANCE IN EXTERNAL REFERENCE MODE CMRR vs FREQUENCY
Figure 58. Figure 59.
36 Copyright © 2007, Texas Instruments Incorporated
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