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SNR − dBFS
67
68
69
70
71
72
73
74
75
76
78
80
82
84
86
88
90
92
0.5 1.0 1.5 2.0 2.5 3.0
SFDR − dBc
Input Clock Amplitude − V
PP
G031
SNR
SFDR
f
IN
= 50.1 MHz
SNR − dBFS
69
70
71
72
73
74
Input Clock Duty Cycle − %
72
74
76
78
80
82
35 40 45 50 55 60 65
SFDR − dBc
G032
SNR
SFDR
f
IN
= 20.1 MHz
f
S
− Sampling Frequency − MSPS
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0 20 40 60 80
P
D
− Power Dissipation − W
G051
LVDD
AVDD
Output Code
0
5
10
15
20
25
30
35
40
2036 2037 2038 2039 2040 2041 2042 2043 2044
Occurence − %
G034
RMS (LSB) = 0.407
f − Frequency − MHz
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 50 100 150 200 250 300
CMRR − Common-Mode Rejection Ratio − dBc
G018
SNR − dBFS
65
67
69
71
73
75
V
VCM
− VCM Voltage − V
86
88
90
92
94
96
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70
f
IN
= 50.1 MHz
External Reference Mode
SFDR − dBc
G035
SNR
SFDR
ADS6424
ADS6423
ADS6422
SLAS532A – MAY 2007 – REVISED JUNE 2007
ADS6423 (F
srated
= 80 MSPS) (continued)
PERFORMANCE vs CLOCK AMPLITUDE PERFORMANCE vs CLOCK DUTY CYCLE
Figure 36. Figure 37.
OUTPUT NOISE HISTOGRAM WITH
POWER DISSIPATION vs SAMPLING FREQUENCY INPUTS TIED TO COMMON-MODE
Figure 38. Figure 39.
PERFORMANCE IN EXTERNAL REFERENCE MODE CMRR vs FREQUENCY
Figure 40. Figure 41.
Copyright © 2007, Texas Instruments Incorporated 33
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