Datasheet

www.ti.com
ADS6424
ADS6423
ADS6422
SLAS532A – MAY 2007 – REVISED JUNE 2007
PIN ASSIGNMENTS (1-WIRE INTERFACE) (continued)
PINS
NO. OF
I/O DESCRIPTION
PINS
NAME NO.
IND_P, IND_M 37,38 I 2 Differential input signal pair, channel D. If unused, the pins should be tied to VCM. Do not float.
CAP 5 1 Connect 2-nF capacitance from pin to ground
This pin functions as serial interface clock input when RESET is low.
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes (along with
SCLK 44 I 1
SDATA). Refer to Table 5 for description.
This pin has an internal pull-down resistor.
This pin functions as serial interface data input when RESET is low.
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes (along with
SDATA 43 I 1
SCLK). Refer to Table 5 for description.
This pin has an internal pull-down resistor.
This pin functions as serial interface enable input when RESET is low.
When RESET is high, it controls coarse gain and internal/external reference modes. Refer to
SEN 42 I 1
Table 6 for description.
This pin has an internal pull-up resistor.
Serial interface reset input.
When using the serial interface mode, the user MUST initialize internal registers through hardware
RESET by applying a high-going pulse on this pin or by using software reset option. Refer to the
RESET 6 I 1
Serial Interface section. In parallel interface mode, tie RESET permanently high. (SCLK, SDATA
and SEN function as parallel control pins in this mode).
The pin has an internal pull-down resistor to ground.
PDN 41 I 1 Global power down control pin.
Parallel input pin. It controls 1-wire or 2-wire interface and DDR or SDR bit clock selection. Refer to
CFG1 30 I 1 Table 8 for description.
Tie to ground for 1-wire interface with DDR bit clock.
Parallel input pin. It controls 12x or 14x serialization and SDR bit clock capture edge. Refer to
CFG2 29 I 1 Table 9 for description.
For 12x serialization with DDR bit clock, tie to ground or AVDD.
CFG3 28 I 1 RESERVED pin - TIE to ground.
Parallel input pin. It controls data format and MSB or LSB first modes. Refer to Table 11 for
CFG4 21 I 1
description.
Internal reference mode – common-mode voltage output
VCM 22 I/O 1 External reference mode – reference input. The voltage forced on this pin sets the internal
reference.
OUTPUT PINS
DA_P,DA_M 62,63 O 2 Channel A differential LVDS data output pair
DB_P,DB_M 60,61 O 2 Channel B differential LVDS data output pair
DC_P,DC_M 52,53 O 2 Channel C differential LVDS data output pair
DD_P,DD_M 50,51 O 2 Channel D differential LVDS data output pair
DCLKP,DCLKM 57,58 O 2 Differential bit clock output pair
FCLKP,FCLKM 55,56 O 2 Differential frame clock output pair
UNUSED 1-4,45-48 8 These pins are unused in the 1-wire interface. Do not connect
NC 20 1 Do Not Connect
Connect to ground plane using multiple vias. See Board Design Considerations in application
PAD 0 1
section.
Copyright © 2007, Texas Instruments Incorporated 27
Submit Documentation Feedback