Datasheet

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ADS6424
ADS6423
ADS6422
SLAS532A – MAY 2007 – REVISED JUNE 2007
PIN ASSIGNMENTS (2-WIRE INTERFACE) (continued)
PINS
NO. OF
I/O DESCRIPTION
PINS
NAME NO.
INB_P, INB_M 15,14 I 2 Differential input signal pair, channel B. If unused, the pins should be tied to VCM. Do not float.
INC_P, INC_M 34,35 I 2 Differential input signal pair, channel C. If unused, the pins should be tied to VCM. Do not float.
IND_P, IND_M 37,38 I 2 Differential input signal pair, channel D. If unused, the pins should be tied to VCM. Do not float.
CAP 5 1 Connect 2-nF capacitor from pin to ground
This pin functions as serial interface clock input when RESET is low.
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes (along with
SCLK 44 I 1
SDATA). Refer to Table 5 for description.
This pin has an internal pull-down resistor.
This pin functions as serial interface data input when RESET is low.
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes (along with
SDATA 43 I 1
SCLK). Refer to Table 5 for description.
This pin has an internal pull-down resistor.
This pin functions as serial interface enable input when RESET is low.
When RESET is high, it controls coarse gain and internal/external reference modes. Refer to Table 6 for
SEN 42 I 1
description.
This pin has an internal pull-up resistor.
Serial interface reset input.
When using the serial interface mode, the user MUST initialize internal registers through hardware
RESET by applying a high-going pulse on this pin or by using software reset option. Refer to the Serial
RESET 6 I 1
Interface section. In parallel interface mode, tie RESET permanently high. (SCLK, SDATA and SEN
function as parallel control pins in this mode).
The pin has an internal pull-down resistor to ground.
PDN 41 I 1 Global power down control pin.
Parallel input pin. It controls 1-wire or 2-wire interface and DDR or SDR bit clock selection. Refer to
CFG1 30 I 1 Table 8 for description.
Tie to AVDD for 2-wire interface with DDR bit clock.
Parallel input pin. It controls 12x or 14x serialization and SDR bit clock capture edge. Refer to Table 9
CFG2 29 I 1 for description.
For 12x serialization with DDR bit clock, tie to ground or AVDD.
CFG3 28 I 1 RESERVED pin - TIE to ground.
CFG4 21 I 1 Parallel input pin. It controls data format and MSB or LSB first modes. Refer to Table 11 for description.
Internal reference mode – common-mode voltage output
VCM 22 I/O 1
External reference mode – reference input. The voltage forced on this pin sets the internal reference.
OUTPUT PINS
DA0_P,DA0_M 3,4 O 2 Channel A differential LVDS data output pair, wire 0
DA1_P,DA1_M 1,2 O 2 Channel A differential LVDS data output pair, wire 1
DB0_P,DB0_M 62,63 O 2 Channel B differential LVDS data output pair, wire 0
DB1_P,DB1_M 60,61 O 2 Channel B differential LVDS data output pair, wire 1
DC0_P,DC0_M 52,53 O 2 Channel C differential LVDS data output pair, wire 0
DC1_P,DC1_M 50,51 O 2 Channel C differential LVDS data output pair, wire 1
DD0_P,DD0_M 47,48 O 2 Channel D differential LVDS data output pair, wire 0
DD1_P,DD1_M 45,46 O 2 Channel D differential LVDS data output pair, wire 1
DCLKP,DCLKM 57,58 O 2 Differential bit clock output pair
FCLKP,FCLKM 55,56 O 2 Differential frame clock output pair
NC 20 1 Do Not Connect
PAD 0 1 Connect to ground plane using multiple vias. See Board Design Considerations in application section.
Copyright © 2007, Texas Instruments Incorporated 25
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