Datasheet

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PIN CONFIGURATION (2-WIRE INTERFACE)
PAD
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
ADS642x
RGCPACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DA1_P
DA1_M
DA0_P
DA0_M
CAP
RESET
LVDD
AGND
AVDD
AGND
INA_M
INA_P
AGND
INB_M
INB_P
AGND
AVDD
AGND
AVDD
NC
CFG4
VCM
AGND
CLKP
CLKM
AGND
AVDD
CFG3 CFG2 CFG1
AGND
A
VDD
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31
50
32
49
DD0_M
DD0_P
DD1_M
DD1_P
SCLK
SDATA
SEN
PDN
AVDD
AGND
IND_M
IND_P
AGND
INC_M
INC_P
AGND
LVDD DB0_M DB0_P DB1_M DB1_P LGND DCLKM DCLKP FCLKM FCLKP LGND DC0_M DC0_P DC1_M DC1_P LVDD
P0056-06
ADS6424
ADS6423
ADS6422
SLAS532A – MAY 2007 – REVISED JUNE 2007
PIN ASSIGNMENTS (2-WIRE INTERFACE)
PINS
NO. OF
I/O DESCRIPTION
PINS
NAME NO.
SUPPLY AND GROUND PINS
9,17,19,27,32
AVDD 6 Analog power supply
,40
8,10,13,16,
AGND 18, 23, 26, 11 Analog ground
31,33,36,39
LVDD 7,49,64 3 Digital power supply
LGND 54,59 2 Digital ground
INPUT PINS
CLKP, CLKM 24,25 I 2 Differential input clock pair
INA_P, INA_M 12,11 I 2 Differential input signal pair, channel A. If unused, the pins should be tied to VCM. Do not float.
24 Copyright © 2007, Texas Instruments Incorporated
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