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SLAS532A – MAY 2007 – REVISED JUNE 2007

D4 Bit clock capture edge (only when SDR bit clock is selected, D1 = 1)

0 Capture data with falling edge of bit clock

1 Capture data with rising edge of bit clock

D5 <COARSE GAIN> Coarse gain control

0 0 dB coarse gain

1 3.5dB coarse gain (full-scale range = 1.34 V

)

D6 MSB or LSB first selection

0 MSB First

1 LSB First

D7 Byte/bit wise outputs (only when 2-wire is selected)

0 Byte wise

1 Bit wise

D10 <OVRD> Over-ride bit. All the functions in register 0x0D can also be controlled using the

parallel control pins. By setting bit <OVRD> = 1, the contents of register 0x0D will over-ride

the settings of the parallel pins.

0 Disable over-ride

1 Enable over-ride

Table 19. Serial Register G

BITS

ADDRESS

A4 - A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

LVDS INTERNAL TERMINATION BIT AND WORD CLOCKS LVDS CURRENT SETTINGS LVDS CURRENT DOUBLE

D0 <CURR DOUBLE> LVDS current double for data outputs

0 Nominal LVDS current, as set by <D5 … D2>

1 Double the nominal value

D1 <CURR DOUBLE> LVDS current double for bit and word clock outputs

0 Nominal LVDS current, as set by <D5 … D2>

1 Double the nominal value

D3-D2 <LVDS CURR> LVDS current setting for data outputs

00 3.5 mA

01 4 mA

10 2.5 mA

11 3 mA

D5-D4 <LVDS CURR> LVDS current setting for bit and word clock outputs

00 3.5 mA

01 4 mA

10 2.5 mA

11 3 mA

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