Datasheet

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ADS6424
ADS6423
ADS6422
SLAS532A – MAY 2007 – REVISED JUNE 2007
Table 14. Serial Register B
REGISTER
BITS
ADDRESS
A4 - A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
<CLKIN GAIN>
04 0 0 0 0 0 0
INPUT CLOCK BUFFER GAIN CONTROL
D6 - D2 <CLKIN GAIN> Input clock buffer gain control
11000 Gain 0, minimum gain
00000 Gain 1, default gain after reset
01100 Gain 2
01010 Gain 3
01001 Gain 4
01000 Gain 5, maximum gain
Table 15. Serial Register C
REGISTER
BITS
ADDRESS
A4 - A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
<DF>
DATA
DORMAT 2S <PATTERNS>
00 0 0 0 0 0 0 0
COMP OR TEST PATTERNS
STRAIGHT
BINARY
D7 - D5 <PATTERNS> Capture test patterns
000 Normal ADC operation
001 Output all zeros
010 Output all ones
011 Output toggle pattern
100 Unused
101 Output custom pattern (contents of CUSTOM pattern registers 0x0B and 0x0C)
110 Output DESKEW pattern (serial stream of 1010..)
111 Output SYNC pattern
D9 <DF> Data format selection
0 2s Complement format
1 Straight binary format
20 Copyright © 2007, Texas Instruments Incorporated
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