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SERIAL INTERFACE TIMING CHARACTERISTICS
RESET TIMING
T0108-03
t
1
t
3
t
2
PowerSupply
AVDD,LVDD
RESET
SEN
ADS6424
ADS6423
ADS6422
SLAS532A – MAY 2007 – REVISED JUNE 2007
Typical values at 25 ° C, min and max values across the full temperature range T
MIN
= – 40 ° C to T
MAX
= 85 ° C, AVDD = LVDD =
3.3 V, unless otherwise noted.
PARAMETER MIN TYP MAX UNIT
f
SCLK
SCLK Frequency, f
SCLK
= 1/t
SCLK
> DC 20 MHz
t
SLOADS
SEN to SCLK Setup time 25 ns
t
SLOADH
SCLK to SEN Hold time 25 ns
t
DSU
SDATA Setup time 25 ns
t
DH
SDATA Hold time 25 ns
Time taken for register write to take effect after 16th SCLK falling edge 100 ns
Typical values at 25 ° C, min and max values across the full temperature range T
MIN
= – 40 ° C to T
MAX
= 85 ° C, AVDD = LVDD =
3.3 V, unless otherwise noted.
PARMATER CONDITIONS MIN TYP MAX UNIT
t
1
Power-on delay time Delay from power-up of AVDD and LVDD to RESET pulse active 5 ms
t
2
Reset pulse width Pulse width of active RESET signal 10 ns
t
3
Register write delay time Delay from RESET disable to SEN active 25 ns
t
PO
Power-up delay time Delay from power-up of AVDD and LVDD to output stable 6.5 ms
Figure 5. Reset Timing
Copyright © 2007, Texas Instruments Incorporated 17
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