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(3/8) AVDD
(3/8) AVDD
ToParallelPin
3R
AVDD
AVDDGND
GND
3R
2R
(5/8) AVDD
(5/8) AVDD
ADS6424
ADS6423
ADS6422
SLAS532A – MAY 2007 – REVISED JUNE 2007
Table 4. Priority Between Parallel Pins and Serial Registers
FUNCTIONS
PIN PRIORITY
SUPPORTED
As described in Table 8 Register bits can control the modes only if the register bit <OVRD> is high. If <OVRD> is
CFG1 to CFG4
to Table 11 low, then the control voltage on these parallel pins determines the function.
Register bit <PDN GLOBAL> controls global power down only if PDN pin is low. If PDN is
PDN Global Power Down
high, device is in global power down mode.
Coarse gain setting is controlled by bit <COARSE GAIN> only if the <OVRD> bit is high.
Else, it is in default setting of 0 dB gain.
SEN Serial Interface Enable
Internal/External reference setting is determined by bit <REF>.
Serial Interface Clock Register bits <PATTERN> control the sync and deskew output patterns.
SCLK, SDATA and Serial Interface Data
Power down is determined by bit <PDN GLOBAL>.
pins
Figure 3. Simple Scheme to Configure Parallel Pins
14 Copyright © 2007, Texas Instruments Incorporated
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