Datasheet

www.ti.com
TIMING SPECIFICATIONS
(1)
ADS6424
ADS6423
ADS6422
SLAS532A – MAY 2007 – REVISED JUNE 2007
Typical values are at 25 ° C, min and max values are across the full temperature range T
MIN
= – 40 ° C to T
MAX
= 85 ° C, AVDD =
LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 V
PP
clock amplitude, C
L
= 5 pF
(2)
, I
O
= 3.5 mA,
R
L
= 100 Ω
(3)
, no internal termination, unless otherwise noted.
ADS6424 ADS6423 ADS6422
TEST
F
s
= 105 MSPS F
s
= 80 MSPS F
s
= 65 MSPS
PARAMETER UNIT
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
t
J
Aperture jitter Uncertainty in the
250 250 250 fs rms
sampling instant
Interface: 2-wire, DDR bit clock, 14x
serialization
From data
Data setup time
(4)
t
su
cross-over to bit 0.45 0.65 0.65 0.85 0.8 1.1 ns
(5) (6)
clock cross-over
From bit clock
Data hold time
(4)
t
h
cross-over to data 0.5 0.7 0.7 0.9 0.8 1.1 ns
(5) (6)
cross-over
Input clock rising
Clock
edge cross-over to
t
pd_clk
propagation delay 3.4 4.4 5.4 3.4 4.4 5.4 3.4 4.4 5.4 ns
frame clock rising
(6)
edge cross-over
Bit clock
cycle-cycle jitter 350 350 350 ps pp
(5)
Frame clock
cycle-cycle jitter 75 75 75 ps pp
(5)
Below specifications apply for 5 MSPS ≤ Sampling freq ≤ 105 MSPS and all interface options
Delay from input
clock rising edge to
t
A
Aperture delay 1 2 3 1 2 3 1 2 3 ns
the actual sampling
instant
Aperture delay Channel-channel
– 250 ± 80 250 – 250 ± 80 250 – 250 ± 80 250 ps
variation within same device
Time for a sample
to propagate to Clock
ADC Latency
(7)
12 12 12
ADC outputs, see cycles
Figure 1
Time to valid data
after coming out of 100 100 100 μ s
global power down
Time to valid data
Wake up time after input clock is 100 100 100 μ s
re-started
Time to valid data
after coming out of 200 200 200 clock cycles
channel standby
From – 100 mV to
t
RISE
Data rise time 50 100 200 50 100 200 50 100 200 ps
+100 mV
From +100 mV to
t
FALL
Data fall time 50 100 200 50 100 200 50 100 200 ps
– 100 mV
(1) Timing parameters are ensured by design and characterization and not tested in production.
(2) C
L
is the external single-ended load capacitance between each output pin and ground.
(3) I
o
refers to the LVDS buffer current setting; R
L
is the external differential load resistance between the LVDS output pair.
(4) Timing parameters are measured at the end of a 2 inch pcb trace (100- Ω characteristic impedance) terminated by R
L
and C
L
.
(5) Setup and hold time specifications take into account the effect of jitter on the output data and clock.
(6) Refer to Output Timings in application section for timings at lower sampling frequencies and other interface options.
(7) Note that the total latency = ADC latency + internal serializer latency. The serializer latency depends on the interface option selected as
listed in Table 27 .
10 Copyright © 2007, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6424 ADS6423 ADS6422