Datasheet

ADS62P45, ADS62P44
ADS62P43, ADS62P42
www.ti.com SLAS561C –JULY 2007– REVISED FEBRUARY 2012
TIMING CHARACTERISTICS – LVDS AND CMOS MODES
(1)
(continued)
Typical values are specified at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock,
1.5 V
PP
clock amplitude, C
L
= 5 pF
(2)
, I
O
= 3.5 mA, R
L
= 100 Ω
(3)
, no internal termination, unless otherwise noted.
Min and max values are specified across the full temperature range T
MIN
= –40°C to T
MAX
= 85°C, AVDD = 3.0 V to 3.6 V,
unless otherwise specified.
ADS62P45 ADS62P44 ADS62P43 ADS62P42
F
S
= 125 MSPS F
S
= 105 MSPS F
S
= 80 MSPS F
S
= 65 MSPS
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
PARALLEL CMOS MODE, DRVDD = 2.5 V to 3.6 V, default output buffer drive strength
(7)
Data setup Data valid
(8)
to 50% of
t
su
2.0 3.5 2.8 4.3 4.3 5.8 5.7 7.2 ns
time
(5)
CLKOUT rising edge
50% of CLKOUT
Data hold
t
h
rising edge to data 2.0 3.5 2.7 4.2 4.2 5.7 5.6 7.1 ns
time
(5)
becoming invalid
(8)
Clock Input clock rising edge
t
PDI
propagation zero-cross to 50% of 5.8 7.3 8.8 5.8 7.3 8.8 5.8 7.3 8.8 5.8 7.3 8.8 ns
delay CLKOUT rising edge
Duty cycle of output
Output clock
clock (CLKOUT) 45% 53% 60% 45% 53% 60% 45% 53% 60% 45% 53% 60%
duty cycle
10 ≤ Fs ≤ 125 MSPS
Rise time measured
from 20% to 80% of
Data rise
DRVDD
t
r
time
Fall time measured 1.0 1.8 2.5 1.0 1.8 2.5 1.0 1.8 2.5 1.0 1.8 2.5 ns
t
f
Data fall
from 80% to 20% of
time
DRVDD
1 ≤ Fs ≤ 125 MSPS
Rise time measured
from 20% to 80% of
Output clock
DRVDD
t
CLKRISE
rise time
Fall time measured 1.0 1.8 2.5 1.0 1.8 2.5 1.0 1.8 2.5 1.0 1.8 2.5 ns
t
CLKFALL
Output clock
from 80% to 20% of
fall time
DRVDD
1 ≤ Fs ≤ 125 MSPS
PARALLEL CMOS INTERFACE, DRVDD = 1.8V, maximum buffer drive strength
(9)
Input clock rising edge
t
START
Start time to data getting valid 8.5 7.5 5.5 3.6 ns
(10) (11)
Width of valid data
t
DV
3.3 6.0 5.0 7.5 8.0 10.5 10.5 13.5 ns
window
PARALLEL CMOS INTERFACE, DRVDD = 1.8V, MULTIPLEXED MODE, maximum buffer drive strength
F
S
= 65 MSPS F
S
= 40 MSPS
UNIT
MIN TYP MAX MIN TYP MAX
Input clock falling
Start time, edge to channel A
t
START_CHA
0.8 2.3 –4.5 –3 ns
channel A data getting valid
(10)
(11)
Data valid, Width of valid data
t
DV_CHA
5.4 6.4 10.3 11.3 ns
channel A window
Input clock rising edge
Start time,
t
START_CHB
to channel B data 1.1 2.4 –4.1 –2.5 ns
channel B
getting valid
(10) (11)
Data valid, Width of valid data
t
DV_CHB
5 6 9.7 10.7 ns
channel B window
(7) For DRVDD < 2.2 V, it is recommended to use external clock for data capture and NOT the device output clock signal (CLKOUT). See
Parallel CMOS interface in application section.
(8) Data valid refers to logic high of 2 V (1.7 V) and logic low of 0.8 V (0.7 V) for DRVDD = 3.3 V (2.5 V).
(9) For DRVDD < 2.2 V, output clock cannot be used for data capture. A delayed version of the input clock can be used, that gives the
desired setup & hold times at the receiving chip
(10) Data valid refers to LOGIC HIGH of 1.26 V and LOGIC LOW of 0.54 V for DRVDD = 1.8 V
(11) Measured from zero-crossing of input clock having 50% duty cycle
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