Datasheet

ADS62P45, ADS62P44
ADS62P43, ADS62P42
SLAS561C –JULY 2007– REVISED FEBRUARY 2012 www.ti.com
TIMING CHARACTERISTICS – LVDS AND CMOS MODES
(1)
Typical values are specified at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock,
1.5 V
PP
clock amplitude, C
L
= 5 pF
(2)
, I
O
= 3.5 mA, R
L
= 100 Ω
(3)
, no internal termination, unless otherwise noted.
Min and max values are specified across the full temperature range T
MIN
= –40°C to T
MAX
= 85°C, AVDD = 3.0 V to 3.6 V,
unless otherwise specified.
ADS62P45 ADS62P44 ADS62P43 ADS62P42
F
S
= 125 MSPS F
S
= 105 MSPS F
S
= 80 MSPS F
S
= 65 MSPS
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
Aperture
t
a
0.7 1.5 2.5 0.7 1.5 2.5 0.7 1.5 2.5 0.7 1.5 2.5 ns
delay
| ta1 - ta2 | ,
Channel-to-channel
50 50 50 50
within the same
Aperture
device
delay ps
| ta1 - ta2 | ,
matching
Channel-to-channel
450 450 450 450
across two devices at
same temperature
Aperture
t
j
150 150 150 150 fs rms
jitter
from global power
15 50 15 50 15 50 15 50 μs
down
Wake-up
time from standby 15 50 15 50 15 50 15 50 μs
(to valid
from output CMOS 100 200 100 200 100 200 100 200 ns
data)
buffer
LVDS 200 500 200 500 200 500 200 500 ns
disable
default, after reset 14 14 14 14 clock cycles
with low latency mode
10 10 10 10 clock cycles
Latency enabled
with decimation filter
15 15 15 15 clock cycles
enabled
DDR LVDS MODE
(4)
, DRVDD = 3.0 V to 3.6 V
Data valid
(6)
to
Data setup
t
su
zero-cross of 0.6 1.5 1.0 2.3 2.4 3.8 3.8 5.2 ns
time
(5)
CLKOUTP
Zero-cross of
Data hold
t
h
CLKOUTP to data 1.0 2.3 1.0 2.3 1.0 2.3 1.0 2.3 ns
time
(5)
becoming invalid
(6)
Input clock rising edge
Clock
zero-cross to output
t
PDI
propagation 3.5 5.5 7.5 3.5 5.5 7.5 3.5 5.5 7.5 3.5 5.5 7.5 ns
clock rising edge
delay
zero-cross
Duty cycle of
LVDS bit differential clock,
clock duty (CLKOUTP- 46% 50% 53% 46% 50% 53% 46% 50% 53% 46% 50% 53%
cycle CLKOUTM)
10 ≤ Fs ≤ 125 MSPS
Rise time measured
from –50 mV to 50
Data rise
mV
t
r
time
Fall time measured 70 100 170 70 100 170 70 100 170 70 100 170 ps
t
f
Data fall
from 50 mV to –50
time
mV
1 ≤ Fs ≤ 125 MSPS
Rise time measured
from –50 mV to 50
Output clock
mV
t
CLKRISE
rise time
Fall time measured 70 100 170 70 100 170 70 100 170 70 100 170 ps
t
CLKFALL
Output clock
from 50 mV to –50
fall time
mV
1 ≤ Fs ≤ 125 MSPS
(1) Timing parameters are specified by design and characterization and not tested in production.
(2) C
L
is the effective external single-ended load capacitance between each output pin and ground.
(3) I
O
refers to the LVDS buffer current setting; R
L
is the differential load resistance between the LVDS output pair.
(4) Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and the load.
(5) Setup and hold time specifications take into account the effect of jitter on the output data and clock.
(6) Data valid refers to logic high of +100 mV and logic low of –100 mV.
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