Datasheet

ADS62P45, ADS62P44
ADS62P43, ADS62P42
SLAS561C –JULY 2007– REVISED FEBRUARY 2012 www.ti.com
REVISION HISTORY
Changes from Revision A (February 2008) to Revision B Page
• Added Aperature delay matching to TIMING REQUIREMENTS — LVDS AND CMOS MODES ........................................ 8
• Added t
START
description to TIMING REQUIREMENTS — LVDS AND CMOS MODES ..................................................... 9
• Added t
DV
description to TIMING REQUIREMENTS — LVDS AND CMOS MODES .......................................................... 9
• Added t
START_CHA
description to TIMING REQUIREMENTS — LVDS AND CMOS MODES ............................................... 9
• Added t
DV_CHA
description to TIMING REQUIREMENTS — LVDS AND CMOS MODES .................................................... 9
• Added t
START_CHB
description to TIMING REQUIREMENTS — LVDS AND CMOS MODES ............................................... 9
• Added t
DV_CHB
description to TIMING REQUIREMENTS — LVDS AND CMOS MODES .................................................... 9
• Changed Figure 3 CMOS Mode Timing ............................................................................................................................. 12
• Added Figure 4 Multiplexed Mode Timing (CMOS only) .................................................................................................... 12
• Added text to USING PARALLEL INTERFACE CONTROL ONLY section description ..................................................... 13
• Added voltage values to Table 4 ........................................................................................................................................ 14
• Added voltage values to Table 5 ........................................................................................................................................ 14
• Changed Channel A and B powered down to Power down global in Table 6 .................................................................... 14
• Changed DB10 to DB0 to DB13 to DB0 inTable 6 ............................................................................................................. 14
• Added Serial Register Readout section .............................................................................................................................. 17
• Added SERIAL READOUT to register address 00 in Table 7 ............................................................................................ 20
• Added SERIAL READOUT to register address 00 description ........................................................................................... 21
• Changed register address 14, bits D2-D0 111 description from DA10 to DA0 to DB13 to DB0 pins ................................ 23
• Changed pin 56 from NC to SDOUT in CMOS interface pinout ......................................................................................... 28
• Changed pin 56 from NC to SDOUT and added SDOUT description in Pin Assignments (CMOS INTERFACE) ............ 29
• Changed Channel A and B powered down to Global power down in Table 21 ................................................................. 55
• Changed DA13 to DA0 to DB13 to DB0 in Table 21 .......................................................................................................... 55
• Changed DB0-DB10 to DB0-DB13 in Multiplexed Output Mode description ..................................................................... 60
• Changed DA0-DA10 to DA0-DA13 in Multiplexed Output Mode description ..................................................................... 60
Changes from Revision B (May 2009) to Revision C Page
• Changed label positions for DDR LVDS Output Data DXP, DXM in Figure 1 .................................................................... 11
• Changed D3 for register 16 ................................................................................................................................................ 24
• Changed pins 29, 30 and 19, 20 in CMOS interface pinout ............................................................................................... 28
• Changed pins 29, 30 in Pin Assignments CMOS INTERFACE ......................................................................................... 29
• Changed pins 19, 20 in Pin Assignments CMOS INTERFACE ......................................................................................... 29
• Changed pins 29, 30 and 19, 20 in LVDS interface pinout ................................................................................................ 30
• Changed pins 29, 30 in Pin Assignments LVDS INTERFACE ........................................................................................... 30
• Changed pins 19, 20 in Pin Assignments LVDS INTERFACE ........................................................................................... 30
• Changed rising edge to falling edge and falling edge to rising edge in paragraph after Figure 95. ................................... 57
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