Datasheet

ADS62P45, ADS62P44
ADS62P43, ADS62P42
www.ti.com SLAS561C –JULY 2007– REVISED FEBRUARY 2012
ELECTRICAL CHARACTERISTICS (continued)
Typical values are at 25°C, AVDD = 3.3V, DRVDD = 1.8 V to 3.3 V, maximum rated sampling frequency, 50% clock duty
cycle, –1 dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces, unless otherwise
noted.
Min and max values are across the full temperature range T
MIN
= –40°C to T
MAX
= 85°C, AVDD = 3.3 V, DRVDD = 3.3 V,
unless otherwise noted.
ADS62P45 ADS62P44 ADS62P43 ADS62P42
F
S
= 125 MSPS F
S
= 105 MSPS F
S
= 80 MSPS F
S
= 65 MSPS
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
IMD
2-Tone F1 = 185 MHz, F2 = 190 MHz
88 87 92 92 dBFS
Intermodulation each tone at -7 dBFS
Distortion
Crosstalk Up to 100 MHz 95 95 95 95 dB
Recovery to within 1% (of final
Input Overload clock
value) for 6-dB overload with sine 1 1 1 1
Recovery cycles
wave input
PSRR
AC Power for 100 mVpp signal on AVDD
35 35 35 35 dBc
Supply supply
Rejection Ratio
DIGITAL CHARACTERISTICS
(1)
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1, AVDD = 3.0 V to 3.6 V.
ADS62P45/ADS62P44
PARAMETER TEST CONDITIONS
ADS62P43/ADS62P42
MIN TYP MAX UNIT
DIGITAL INPUTS
RESET, CTRL1, CTRL2, CTRL3, SCLK, SDATA & SEN
(2)
High-level input voltage 2.4 V
Low-level input voltage 0.8 V
High-level input current 33 μA
Low-level input current –33 μA
Input capacitance 4 pF
DIGITAL OUTPUTS
CMOS INTERFACE, DRVDD = 1.65 V to 3.6 V
High-level output voltage DRVDD V
Low-level output voltage 0 V
Output capacitance inside the device, from
Output capacitance 2 pF
each output to ground
DIGITAL OUTPUTS
LVDS INTERFACE, DRVDD = 3.0 V to 3.6 V, I
O
= 3.5 mA, R
L
= 100 Ω
(3)
High-level output voltage 1375 mV
Low-level output voltage 1025 mV
Output differential voltage, |V
OD
| 225 350 mV
V
OS
Output offset voltage, single-ended Common-mode voltage of OUTP, OUTM 1200 mV
Output capacitance inside the device, from
Output capacitance 2 pF
either output to ground
(1) All LVDS and CMOS specifications are characterized, but not tested at production.
(2) SCLK & SEN function as digital input pins when they are used for serial interface programming. When used as parallel control pins,
analog voltage needs to be applied as per Table 4 & Table 5
(3) I
O
refers to the LVDS buffer current setting, R
L
is the differential load resistance between the LVDS output pair.
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Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42