Datasheet

0
14 Bits 14 Bits 14 Bits
14 Bits
Filter Select
CLIPPER
From
ADC
Output
Tooutputbuffers
LVDSorCMOS
DECIMATION
BY 2/4/8
Bypass
Filter
Bypass
Decimation
24 TAP FILTER
- LOWPASS
-HIGHPASS
- BANDPASS
DIGITAL
FILTERandDECIMATION
DIGITAL PROCESSINGBLOCK
GAIN
CORRECTIONFINEGAIN
OFFSET
CORRECTION
GainCorrection
(0.05dBSteps)
FineGain
(0to6dB
0.05dBSteps)
14 Bits 14Bits
Disable
Offset
Correction
FreezeOffset
Correction
OFFSET
ESTIMATION
BLOCK
B0289-01
ADS62P45, ADS62P44
ADS62P43, ADS62P42
www.ti.com SLAS561C –JULY 2007– REVISED FEBRUARY 2012
DETAILS OF DIGITAL PROCESSING BLOCK
Figure 100. Digital Processing Block Diagram
Offset Correction
ADS62P4X has an internal offset correction algorithm that estimates and corrects dc offset up to ±10 mV. The
correction can be enabled using the serial register bit ( OFFSET LOOP EN). Once enabled, the algorithm
estimates the channel offset and applies the correction every clock cycle. The time constant of the correction
loop is a function of the sampling clock frequency. The time constant can be controlled using register bits (
OFFSET LOOP TC) as described in Table 22.
Table 22. Time Constant of Offset Correction Algorithm
<OFFSET LOOP TC> TIME CONSTANT (TC
CLK
), TIME CONSTANT, sec
D6-D5-D4 number of clock cycles (= TC
CLK
× 1/Fs)
(1)
000 2
27
1.1
001 2
26
0.55
010 2
25
0.27
011 2
24
0.13
100 2
28
2.15
101 2
29
4.3
110 2
27
1.1
111 2
27
1.1
(1) Sampling frequency, Fs = 125 MSPS
Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 61
Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42