Datasheet

T0110-02

CLKOUTM

DA0(DB0)

DA2(DB2)

DA4(DB4)

DA6(DB6)

DA8(DB8)

DA10(DB10)

DA12(DB12)

D10

D12

SampleN+1SampleN

D10

D12

D11

D13

D11

D13

CLKOUTP

ADS62P45, ADS62P44

ADS62P43, ADS62P42

SLAS561C –JULY 2007– REVISED FEBRUARY 2012

www.ti.com

Figure 96. DDR LVDS Interface

LVDS Buffer Current Programmability

The default LVDS buffer output current is 3.5 mA. When terminated by 100 Ω, this results in a 350-mV

single-ended voltage swing (700-mV

differential swing). The LVDS buffer currents can also be programmed to

2.5 mA, 4.5 mA, and 1.75 mA ( LVDS CURRENT). In addition, there exists a current double mode, where this

current is doubled for the data and output clock buffers (register bits CURRENT DOUBLE).

LVDS Buffer Internal Termination

An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially

terminated inside the device. The termination resistances available are –300 Ω, 185 Ω, and 150 Ω (nominal with

±20% variation). Any combination of these three terminations can be programmed; the effective termination is

the parallel combination of the selected resistances. This results in eight effective terminations from open (no

termination) to 60 Ω.

The internal termination helps to absorb any reflections coming from the receiver end, improving the signal

integrity. With 100 Ω internal and 100-Ω external termination, the voltage swing at the receiver end is halved

(compared to no internal termination). The voltage swing can be restored by using the LVDS current double

mode. Figure 97 and Figure 98 compare the LVDS eye diagrams without and with 100-Ω internal termination.

With internal termination, the eye looks clean even with 10-pF load capacitance (from each output pin to ground).

The terminations can be programmed using register bits ( LVDS TERMINATION).

Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42