Datasheet

CLKOUTP
CLKOUTM
DA0P
DA0M
DA2P
DA2M
OutputClock
DataBitsD0,D1
DataBitsD2,D3
Pins
DA12P
DA12M
DataBitsD12,D13
14-BitChannel-A
Data
LVDSBuffers
DB0P
DB0M
DB2P
DB2M
DataBitsD0,D1
DataBitsD2,D3
DB12P
DB12M
DataBitsD12,D13
14-BitChannel-B
Data
B0288-01
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ADS62P45, ADS62P44
ADS62P43, ADS62P42
www.ti.com SLAS561C –JULY 2007– REVISED FEBRUARY 2012
CMOS Mode Power Dissipation
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every
output pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock
cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined
by the average number of output bits switching, which is a function of the sampling frequency and the nature of
the analog input signal.
Digital current due to CMOS output switching = C
L
× DRVDD × (N × F
AVG
),
where C
L
= load capacitance, N × F
AVG
= average number of output bits switching.
Figure 81 shows the current with various load capacitances across sampling frequencies at 2 MHz analog input
frequency.
DDR LVDS Interface
The LVDS interface works only with 3.3-V DRVDD supply. In this mode, the 11 data bits of each channel and a
common output clock are available as LVDS (Low Voltage Differential Signal) levels. Two successive data bits
are multiplexed and output on each LVDS differential pair every clock cycle (DDR – Double Data Rate,
Figure 96).
Figure 95. DDR LVDS Outputs
Odd data bits D1, D3, D5, D7, D9 are output at the falling edge of CLKOUTP and even data bits D0, D2, D4, D6,
D8, D10 are output at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP have to be
used to capture all the data bits.
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