Datasheet

DA0
DA1
DA2
DA3
DA12
DA13
CLKOUT
CMOS
OutputBuffers
14-BitChannel-A
Data
DB0
DB1
DB2
DB3
DB12
DB13
14-BitChannel-B
Data
B0287-01
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ADS62P45, ADS62P44
ADS62P43, ADS62P42
SLAS561C –JULY 2007– REVISED FEBRUARY 2012 www.ti.com
DIGITAL OUTPUT INFORMATION
ADS62P4X provides 14-bit data per channel and a common output clock synchronized with the data. The output
interface can be either parallel CMOS or DDR LVDS voltage levels and can be selected using serial register bit
<OUTPUT INTERFACE> or parallel pin SEN.
Parallel CMOS Interface
In the CMOS mode, the output buffer supply (DRVDD) can be operated over a wide range from 1.8 V to 3.3 V
(typical). Each data bit is output on separate pin as CMOS voltage level, every clock cycle (see Figure 94).
For DRVDD > 2.2 V, it is recommended to use the CMOS output clock (CLKOUT) to latch data in the receiving
chip. The rising edge of CLKOUT can be used to latch data in the receiver, even at the highest sampling speed.
It is recommended to minimize the load capacitance seen by data and clock output pins by using short traces to
the receiver. Also, match the output data and clock traces to minimize the skew between them.
For DRVDD < 2.2 V, it is recommended to use external clock (for example, input clock delayed to get desired
setup/hold times).
Figure 94. CMOS Output Interface
Output Buffer Strength Programmability
Switching noise (caused by CMOS output data transitions) can couple into the analog inputs during the instant of
sampling and degrade the SNR. The coupling and SNR degradation increases as the output buffer drive is made
stronger. To minimize this, ADS62P4X CMOS output buffers are designed with controlled drive strength to get
best SNR. The default drive strength also ensures wide data stable window for load capacitances up to 5 pF and
DRVDD supply voltage >2.2 V.
To ensure wide data stable window for load capacitance > 5 pF, there exists option to increase the output data
and clock drive strengths using the serial interface ( DATAOUT STRENGTH and CLKOUT STRENGTH). Note
that for DRVDD supply voltage <2.2 V, it is recommended to use maximum drive strength (for any value of load
capacitance).
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Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42