Datasheet

S0167-06
CLKP
CLKM
DifferentialSine-Wave
orPECL orLVDSClockInput
ADS62P4x
0.1 Fm
0.1 Fm
S0168-10
CLKP
CLKM
CMOSClockInput
ADS62P4x
0.1 Fm
0.1 Fm
ADS62P45, ADS62P44
ADS62P43, ADS62P42
SLAS561C –JULY 2007– REVISED FEBRUARY 2012 www.ti.com
Figure 92. Differential Clock Driving Circuit
Single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF
capacitor, as shown in Figure 93.
Figure 93. Single-Ended Clock Driving Circuit
For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode
noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Bandpass
filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a
non-50% duty cycle clock input.
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Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42