Datasheet

ADS62P45, ADS62P44

ADS62P43, ADS62P42

SLAS561C –JULY 2007– REVISED FEBRUARY 2012

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COARSE GAIN AND PROGRAMMABLE FINE GAIN

ADS62P4X includes gain settings that can be used to get improved SFDR performance (over 0dB gain mode).

For each gain setting, the analog input full-scale range scales proportionally, as shown in Table 20.

The coarse gain is a fixed setting of 3.5 dB and is designed to improve SFDR with little degradation in SNR. The

fine gain is programmable in 0.5 dB steps from 0 to 6 dB; however the SFDR improvement is achieved at the

expense of SNR. So, the programmable fine gain makes it possible to trade-off between SFDR and SNR. The

coarse gain makes it possible to get best SFDR but without losing SNR significantly.

The gains can be programmed using the serial interface (bits COARSE GAIN and FINE GAIN). Note that the

default gain after reset is 0 dB.

Table 20. Full-Scale Range Across Gains

GAIN, dB TYPE FULL-SCALE, V

0 Default after reset 2V

3.5 Coarse (fixed) 1.34

0.5 1.89

1.0 1.78

1.5 1.68

2.0 1.59

2.5 1.50

3.0 1.42

Fine (programmable)

3.5 1.34

4.0 1.26

4.5 1.19

5.0 1.12

5.5 1.06

6.0 1.00

CLOCK INPUT

The clock inputs can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS), with little or

no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM using

internal 5-kΩ resistors as shown in Figure 90. This allows using transformer-coupled drive circuits for sine wave

clock or ac-coupling for LVPECL, LVDS clock sources (Figure 92 and Figure 93).

Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42