Datasheet

ADS62P45, ADS62P44
ADS62P43, ADS62P42
www.ti.com SLAS561C –JULY 2007– REVISED FEBRUARY 2012
ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 v to 3.3 V, maximum rated sampling frequency, 50% clock duty
cycle, –1 dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces, unless otherwise
noted.
Min and max values are across the full temperature range T
MIN
= –40°C to T
MAX
= 85°C, AVDD = 3.3 V, DRVDD = 3.3 V,
unless otherwise noted.
ADS62P45 ADS62P44 ADS62P43 ADS62P42
F
S
= 125 MSPS F
S
= 105 MSPS F
S
= 80 MSPS F
S
= 65 MSPS
PARAMETER UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
RESOLUTION 14 14 14 14 Bits
ANALOG INPUT
Differential input voltage range 2 2 2 2 V
PP
Differential input resistance (dc)
> 1 > 1 > 1 > 1 MΩ
see Figure 84
Differential input capacitance
7 7 7 7 pF
see Figure 85
Analog input bandwidth 450 450 450 450 MHz
Analog input common mode current (per μA/MSP
1.3 1.3 1.3 1.3
input pin of each ADC) S
REFERENCE VOLTAGES
VREFB Internal reference bottom voltage 1 1 1 1 V
VREFT Internal reference top voltage 2 2 2 2 V
V
CM
Common mode output voltage 1.5 1.5 1.5 1.5 V
V
CM
output current capability 4 4 4 4 mA
DC ACCURACY
No missing codes Specified Specified Specified Specified
E
O
Offset error -10 ± 2 10 -10 ± 2 10 -10 ± 2 10 -10 ± 2 10 mV
Offset error temperature coefficient 0.05 0.05 0.05 0.05 mV/°C
There are two sources of gain error – internal reference inaccuracy and channel gain error
E
GREF
Gain error due to internal reference
-2 0.25 2 -2 0.25 2 -2 0.25 2 -2 0.25 2 % FS
inaccuracy alone
E
GCHAN
Gain error of channel alone
(1)
across devices & across channels within a -1 ±0.3 1 -1 ±0.3 1 -1 ±0.3 1 -1 ±0.3 1 % FS
device.
0.00
Channel gain error temperature coefficient 0.005 0.005 0.005 Δ%/°C
5
- ± -
DNL Differential nonlinearity -0.95 ± 0.6 -0.95 ± 0.6 ± 0.5 LSB
0.95 0.5 0.95
INL Integral nonlinearity -5 ± 2.5 5 -5 ± 2.5 5 -5 ± 2 5 -5 ± 2 5 LSB
POWER SUPPLY
I
AVDD
Analog supply current 240 275 215 240 180 200 156 175 mA
No external load
Digital supply current,
17 14 12 10 mA
capacitance
CMOS interface
I
DRVDD
DRVDD = 1.8 V
10-pF external
30 26 22 19 mA
Fin = 2 MHz
(2)
load capacitance
Digital supply current, LVDS interface
I
DRVDD
73 73 73 73 mA
with 100-Ω external termination
P
AVDD
Analog power dissipation 799 908 710 792 594 660 515 578 mW
No external load
31 25 22 18 mW
Digital power dissipation,
capacitance
P
DRVDD
CMOS interface
10-pF external
DRVDD = 1.8 V
(3)
54 47 40 34 mW
load capacitance
Global powerdown 50 75 50 75 50 75 50 75 mW
(1) This is specified by design and characterization; it is not tested in production.
(2) In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency and the
supply voltage (see Figure 81 and CMOS power dissipation in application section).
(3) The maximum DRVDD current depends on the actual load capacitance on the digital output lines. Note that the maximum
recommended load capacitance on each digital output line is 10 pF.
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