Datasheet

f
I
− Input Frequency − MHz
−7
−6
−5
−4
−3
−2
−1
0
1
0 100 200 300 400 500 600
Magnitude − dB
G080
f − Frequency − MHz
0 100 200 300 400 500 600
R − Resistance − kΩ
100
10
0.1
0.01
G081
1
ADS62P45, ADS62P44
ADS62P43, ADS62P42
SLAS561C –JULY 2007– REVISED FEBRUARY 2012 www.ti.com
Figure 83. ADC Analog Bandwidth
Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This improves the common-mode
noise immunity and even order harmonic rejection. A 5-Ω resistor in series with each input pin is recommended
to damp out ringing caused by the package parasitics.
It is also necessary to present low impedance (50 Ω) for the common mode switching currents. This can be
achieved by using two resistors from each input terminated to the common mode voltage (VCM).
In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency
range and matched impedance to the source. While doing this, the ADC input impedance must be considered.
Figure 84 and Figure 85 show the impedance (Zin = Rin || Cin) looking into the ADC input pins.
Figure 84. ADC Analog Input Resistance (Rin) Across Frequency
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Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42