Datasheet

Resr
100 W
Lpkg
2nH»
25 W
Sampling
Capacitor
Csamp
4pF
INP
INM
Cbond
1pF»
50 W
Cpar1
0.8pF
Ron
10 W
Cpar2
1pF
Ron
15 W
Ron
15 W
Cpar2
1pF
50 W
3.2pF
Lpkg
2nH»
25 W
Cbond
1pF»
Resr
100 W
Csamp
4pF
Sampling
Capacitor
Sampling
Switch
Sampling
Switch
RCRFilter
S0322-01
ADS62P45, ADS62P44
ADS62P43, ADS62P42
www.ti.com SLAS561C –JULY 2007– REVISED FEBRUARY 2012
APPLICATION INFORMATION
THEORY OF OPERATION
ADS62P4X is a low power 14-bit dual channel pipeline ADC family fabricated in a CMOS process using switched
capacitor techniques.
The conversion process is initiated by a rising edge of the external input clock. Once the signal is captured by
the input sample and hold, the input sample is sequentially converted by a series of small resolution stages, with
the outputs combined in a digital correction logic block. At every clock edge the sample propagates through the
pipeline resulting in a data latency of 14 clock cycles. The output is available as 14-bit data, in DDR LVDS or
CMOS and coded in either straight offset binary or binary 2s complement format.
ANALOG INPUT
The analog input consists of a switched-capacitor based differential sample and hold architecture.
This differential topology results in very good AC performance even for high input frequencies at high sampling
rates. The INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V, available on
VCM pin. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM +
0.5 V and VCM – 0.5 V, resulting in a 2 V
PP
differential input swing. The maximum swing is determined by the
internal reference voltages REFP (2.5 V nominal) and REFM (0.5 V, nominal).
Figure 82. Analog Input Equivalent Circuit
The input sampling circuit has a high 3-dB bandwidth that extends up to 450 MHz (measured from the input pins
to the sampled voltage).
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Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42