Datasheet

f
S
− Sampling Frequency − MSPS
0
10
20
30
40
50
60
0 25 50 75 100 125
DRV
DD
Current − mA
G079
1.8 V, 5 pF
3.3 V, 5 pF
3.3 V, 10 pF
3.3 V, No Load
1.8 V, No Load
1.8 V, 10 pF
ADS62P45, ADS62P44
ADS62P43, ADS62P42
SLAS561C –JULY 2007– REVISED FEBRUARY 2012 www.ti.com
TYPICAL CHARACTERISTICS – LOW SAMPLING FREQUENCIES (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sine wave input clock, 1.5 V
PP
differential clock amplitude, 50% clock duty
cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted)
DRVDD current (CMOS)
vs
SAMPLING FREQUENCY
across load capacitance at 2 MHz input frequency
Figure 81.
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Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42