Datasheet

f
IN
− Input Frequency − MHz
70
75
80
85
90
95
100
0 25 50 75 100 125 150 175 200
SFDR − dBc
G075
Gain = 0 dB
Gain = 3.5 dB
f
IN
− Input Frequency − MHz
66
68
70
72
74
76
78
80
0 25 50 75 100 125 150 175 200
SNR − dBFS
G076
Gain = 0 dB
Gain = 3.5 dB
f − Frequency − MHz
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 25 50 75 100 125 150 175 200
CMRR − dBc
G077
f
S
− Sampling Frequency − MSPS
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 25 50 75 100 125
P
D
− Power Dissipation − W
G078
LVDS
CMOS
f
IN
= 2.5 MHz
C
L
= 5 pF
ADS62P45, ADS62P44
ADS62P43, ADS62P42
www.ti.com SLAS561C –JULY 2007– REVISED FEBRUARY 2012
TYPICAL CHARACTERISTICS – LOW SAMPLING FREQUENCIES
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sine wave input clock, 1.5 V
PP
differential clock amplitude, 50% clock duty
cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted)
F
S
= 25 MSPS
SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY
Figure 77. Figure 78.
COMMON PLOTS
POWER DISSIPATION
vs
COMMON-MODE REJECTION RATIO vs FREQUENCY SAMPLING FREQUENCY (DDR LVDS and CMOS)
Figure 79. Figure 80.
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