Datasheet

f
IN
− Input Frequency − MHz
76
78
80
82
84
86
88
90
92
94
96
0 25 50 75 100 125 150 175 200
SFDR − dBc
G061
Gain = 0 dB
Gain = 3.5 dB
f
IN
− Input Frequency − MHz
80
82
84
86
88
90
92
94
96
98
0 25 50 75 100 125 150 175 200
SFDR − dBc
G063
Input adjusted to get −1dBFS input
1 dB
0 dB
6 dB
4 dB
5 dB
2 dB
3 dB
f
IN
− Input Frequency − MHz
66
67
68
69
70
71
72
73
74
75
76
0 25 50 75 100 125 150 175 200
SINAD − dBFS
G064
2 dB
5 dB
1 dB
0 dB
3 dB
4 dB
6 dB
Input adjusted to get −1dBFS input
SNR − dBFS
72
73
74
75
76
77
78
79
80
AV
DD
− Supply Voltage − V
SFDR − dBc
G065
SNR
SFDR
f
IN
= 70.1 MHz
DRV
DD
= 3.3 V
83
84
85
86
87
88
89
90
91
3.0 3.1 3.2 3.3 3.4 3.5 3.6
SNR − dBFS
72
73
74
75
76
77
78
79
80
DRV
DD
− Supply Voltage − V
SFDR − dBc
G066
SNR
SFDR
f
IN
= 70.1 MHz
AV
DD
= 3.31 V
85
86
87
88
89
90
91
92
93
3.0 3.1 3.2 3.3 3.4 3.5 3.6
SNR − dBFS
72
73
74
75
76
77
78
T − Temperature − °C
SFDR − dBc
G067
f
IN
= 70.1 MHz
SFDR
80
82
84
86
88
90
92
−40 −20 0 20 40 60 80
SNR
ADS62P45, ADS62P44
ADS62P43, ADS62P42
www.ti.com SLAS561C –JULY 2007– REVISED FEBRUARY 2012
TYPICAL CHARACTERISTICS - ADS62P42 (F
S
= 65 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 V
PP
differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
SFDR vs INPUT FREQUENCY (LVDS interface) SFDR vs INPUT FREQUENCY ACROSS GAINS
Figure 66. Figure 67.
SINAD vs INPUT FREQUENCY ACROSS GAINS PERFORMANCE vs AVDD
Figure 68. Figure 69.
PERFORMANCE vs DRVDD PERFORMANCE vs TEMPERATURE
Figure 70. Figure 71.
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Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42