Datasheet

ADS62P45, ADS62P44
ADS62P43, ADS62P42
SLAS561C –JULY 2007– REVISED FEBRUARY 2012 www.ti.com
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
SUPPLIES
AVDD Analog supply voltage 3 3.3 3.6 V
CMOS interface 1.65 1.8 to 3.3 3.6 V
DRVDD Output buffer supply voltage
(1)
LVDS interface 3 3.3 3.6 V
ANALOG INPUTS
Differential input voltage range 2 V
pp
V
IC
Input common-mode voltage 1.5 ± 0.1 V
Voltage applied on VCM in external reference mode 1.45 1.5 1.55 V
CLOCK INPUT
ADS62P45 1 125
ADS62P44 1 105
Input clock sample rate, F
S
MSPS
ADS62P43 1 80
ADS62P42 1 65
Sine wave, ac-coupled 0.4 1.5
LVPECL, ac-coupled ± 0.8
Input clock amplitude differential
V
pp
(V
CLKP
– V
CLKM
)
LVDS, ac-coupled ± 0.35
LVCMOS, ac-coupled 3.3
Input clock duty cycle 35% 50% 65%
DIGITAL OUTPUTS
DEFAULT
for C
LOAD
≤ 5 pF and DRVDD ≥ 2.2 V
strength
MAXIMUM
Output buffer drive strength
(2)
for C
LOAD
> 5 pF and DRVDD ≥ 2.2 V
strength
MAXIMUM
for DRVDD < 2.2 V
strength
CMOS interface, maximum buffer 10
strength
Maximum external load capacitance from each LVDS interface, without internal 5
C
LOAD
pF
output pin to DRGND termination
LVDS interface, with internal 10
termination
R
LOAD
Differential load resistance (external) between the LVDS output pairs 100 Ω
T
A
Operating free-air temperature -40 85 °C
(1) For easy migration to the next generation, higher sampling speed devices (> 125 MSPS), use 1.8V DRVDD supply.
(2) See Output Buffer Strength Programmability in application section.
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Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42