Datasheet

50
55
60
65
70
75
80
85
90
Input Amplitude − dBFS
SFDR − dBc, dBFS
G032
SNR − dBFS
SFDR (dBc)
SFDR (dBFS)
SNR (dBFS)
30
40
50
60
70
80
90
100
110
−60 −50 −40 −30 −20 −10 0
f
IN
= 20.1 MHz
72
73
74
75
76
77
78
79
80
SFDR − dBc
SNR − dBFS
Input Clock Amplitude − V
PP
G033
78
80
82
84
86
88
90
92
94
0.0 0.5 1.0 1.5 2.0 2.5 3.0
SNR
SFDR
f
IN
= 20.1 MHz
SNR − dBFS
70
71
72
73
74
75
76
77
78
79
Input Clock Duty Cycle − %
SFDR − dBc
G034
SNR
SFDR
f
IN
= 20.1 MHz
76
78
80
82
84
86
88
90
92
94
25 30 35 40 45 50 55 60 65 70 75
Output Code
0
5
10
15
20
25
30
35
40
8171 8172 8173 8174 8175 8176 8177 8178 8179 8180
Occurence − %
G035
RMS = 1.006 LSB
SNR − dBFS
70
72
74
76
78
80
V
VCM
− VCM Voltage − V
SFDR − dBc
G036
76
80
84
88
92
96
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70
f
IN
= 20.1 MHz
External Reference Mode
SNR
SFDR
ADS62P45, ADS62P44
ADS62P43, ADS62P42
SLAS561C –JULY 2007– REVISED FEBRUARY 2012 www.ti.com
TYPICAL CHARACTERISTICS - ADS62P44 (F
S
= 105 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 V
PP
differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
PERFORMANCE vs INPUT AMPLITUDE PERFORMANCE vs CLOCK AMPLITUDE
Figure 38. Figure 39.
OUTPUT NOISE HISTOGRAM WITH
PERFORMANCE vs INPUT CLOCK DUTY CYCLE INPUTS TIED TO COMMON-MODE
Figure 40. Figure 41.
PERFORMANCE IN EXTERNAL REFERENCE MODE
Figure 42.
38 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42