Datasheet

50
55
60
65
70
75
80
85
90
Input Amplitude − dBFS
SFDR − dBc, dBFS
G014
SNR − dBFS
SFDR (dBc)
SFDR (dBFS)
SNR (dBFS)
30
40
50
60
70
80
90
100
110
−60 −50 −40 −30 −20 −10 0
f
IN
= 20.1 MHz
SFDR − dBc
SNR − dBFS
72
73
74
75
76
77
78
79
80
Input Clock Amplitude − V
PP
G015
78
80
82
84
86
88
90
92
94
0.5 1.0 1.5 2.0 2.5 3.0
SNR
SFDR
f
IN
= 20.1 MHz
SNR − dBFS
70
71
72
73
74
75
76
77
78
79
Input Clock Duty Cycle − %
SFDR − dBc
G016
SNR
SFDR
f
IN
= 20.1 MHz
76
78
80
82
84
86
88
90
92
94
30 35 40 45 50 55 60 65 70
Output Code
0
5
10
15
20
25
30
35
40
8171 8172 8173 8174 8175 8176 8177 8178 8179 8180
Occurence − %
G017
RMS = 1.033 LSB
SNR − dBFS
70
72
74
76
78
80
V
VCM
− VCM Voltage − V
SFDR − dBc
G018
83
85
87
89
91
93
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70
f
IN
= 20.1 MHz
External Reference Mode
SNR
SFDR
ADS62P45, ADS62P44
ADS62P43, ADS62P42
www.ti.com SLAS561C –JULY 2007– REVISED FEBRUARY 2012
TYPICAL CHARACTERISTICS - ADS62P45 (F
S
= 125 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 V
PP
differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
PERFORMANCE vs INPUT AMPLITUDE PERFORMANCE vs CLOCK AMPLITUDE
Figure 21. Figure 22.
OUTPUT NOISE HISTOGRAM
PERFORMANCE vs INPUT CLOCK DUTY CYCLE (INPUTS TIED TO COMMON-MODE)
Figure 23. Figure 24.
PERFORMANCE IN EXTERNAL REFERENCE MODE
Figure 25.
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