Datasheet

f
IN
− Input Frequency − MHz
76
78
80
82
84
86
88
90
92
94
0 25 50 75 100 125 150 175 200
SFDR − dBc
G007
Gain = 0 dB
Gain = 3.5 dB
f
IN
− Input Frequency − MHz
78
80
82
84
86
88
90
92
94
96
0 25 50 75 100 125 150 175 200
SFDR − dBc
G009
Input adjusted to get −1dBFS input
1 dB
0 dB
5 dB
6 dB
2 dB
3 dB
4 dB
f
IN
− Input Frequency − MHz
65
66
67
68
69
70
71
72
73
74
75
0 25 50 75 100 125 150 175 200
SINAD − dBFS
G010
2 dB
5 dB
1 dB
0 dB
3 dB
4 dB
6 dB
Input adjusted to get −1dBFS input
SNR − dBFS
72
73
74
75
76
77
78
79
80
AV
DD
− Supply Voltage − V
SFDR − dBc
G011
SNR
SFDR
f
IN
= 70.1 MHz
DRV
DD
= 3.31 V
82
83
84
85
86
87
88
89
90
3.0 3.1 3.2 3.3 3.4 3.5 3.6
SNR − dBFS
72
73
74
75
76
77
78
79
80
DRV
DD
− Supply Voltage − V
SFDR − dBc
G012
SNR
SFDR
f
IN
= 70.1 MHz
AV
DD
= 3.31 V
82
83
84
85
86
87
88
89
90
3.0 3.1 3.2 3.3 3.4 3.5 3.6
SNR − dBFS
72
73
74
75
76
77
78
T − Temperature − °C
SFDR − dBc
G013
f
IN
= 70.1 MHz
SFDR
82
83
84
85
86
87
88
−40 −20 0 20 40 60 80
SNR
ADS62P45, ADS62P44
ADS62P43, ADS62P42
SLAS561C –JULY 2007– REVISED FEBRUARY 2012 www.ti.com
TYPICAL CHARACTERISTICS - ADS62P45 (F
S
= 125 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 V
PP
differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
SFDR vs INPUT FREQUENCY (LVDS interface) SFDR vs INPUT FREQUENCY ACROSS GAINS
Figure 15. Figure 16.
SINAD vs INPUT FREQUENCY ACROSS GAINS PERFORMANCE vs AVDD
Figure 17. Figure 18.
PERFORMANCE vs DRVDD PERFORMANCE vs TEMPERATURE
Figure 19. Figure 20.
34 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42