Datasheet
ADS62P45, ADS62P44
ADS62P43, ADS62P42
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SLAS561C –JULY 2007– REVISED FEBRUARY 2012
Pin Assignments (LVDS INTERFACE) (continued)
PIN NUMBER OF
PIN NAME DESCRIPTION
NUMBER PINS
RESET Serial interface RESET input. 12 1
In serial interface mode, the user must initialize internal registers through hardware
RESET by applying a high-going pulse on this pin or by using software reset (refer to
Serial Interface section).
In parallel interface mode, the user has to tie RESET pin permanently high. (SCLK,
SDATA and SEN are used as parallel pin controls in this mode) The pin has an internal
100-kΩ pull-down resistor.
SCLK This pin functions as serial interface clock input when RESET is low. 13 1
It functions as analog control pin when RESET is tied high and controls coarse gain
and internal/external reference selection. See Table 4 for details.
The pin has an internal pull-down resistor to ground.
SDATA This pin functions as serial interface data input when RESET is low. The pin has an 14 1
internal pull-down resistor to ground.
SEN This pin functions as serial interface enable input when RESET is low. 15 1
It functions as analog control pin when RESET is tied high and controls the output
interface (LVDS/CMOS) and data format selection. See Table 5 for details.
The pin has an internal pull-up resistor to AVDD.
CTRL1 These are digital logic input pins. Together they control various power down and 35 1
multiplexed mode. See Table 6 for details.
CTRL2 36 1
CTRL3 37 1
DA0P Channel A Differential output data D0 and D1 multiplexed, true 41 1
DA0M Channel A Differential output data D0 and D1 multiplexed, complement 40 1
DA2P Channel A Differential output data D2 and D3 multiplexed, true 43 1
DA2M Channel A Differential output data D2 and D3 multiplexed, complement 42 1
DA4P Channel A Differential output data D4 and D5 multiplexed, true 45 1
DA4M Channel A Differential output data D4 and D5 multiplexed, complement 44 1
DA6P Channel A Differential output data D6 and D7 multiplexed, true 47 1
DA6M Channel A Differential output data D6 and D7 multiplexed, complement 46 1
DA8P Channel A Differential output data D8 and D9 multiplexed, true 51 1
DA8M Channel A Differential output data D8 and D9 multiplexed, complement 50 1
DA10P Channel A Differential output data D10 and D11 multiplexed, true 53 1
DA10M Channel A Differential output data D10 and D11 multiplexed, complement 52 1
DA12P Channel A Differential output data D12 and D13 multiplexed, true 55 1
DA12M Channel A Differential output data D12 and D13 multiplexed, complement 54 1
CLKOUTP Differential output clock, true 57 1
CLKOUTM Differential output clock, complement 56 1
DB0P Channel B Differential output data D0 and D1 multiplexed, true 61 1
DB0M Channel B Differential output data D0 and D1 multiplexed, complement 60 1
DB2P Channel B Differential output data D2 and D3 multiplexed, true 63 1
DB2M Channel B Differential output data D2 and D3 multiplexed, complement 62 1
DB4P Channel B Differential output data D4 and D5 multiplexed, true 3 1
DB4M Channel B Differential output data D4 and D5 multiplexed, complement 2 1
DB6P Channel B Differential output data D6 and D7 multiplexed, true 5 1
DB6M Channel B Differential output data D6 and D7 multiplexed, complement 4 1
DB8P Channel B Differential output data D8 and D9 multiplexed, true 7 1
DB8M Channel B Differential output data D8 and D9 multiplexed, complement 6 1
DB10P Channel B Differential output data D10 and D11 multiplexed, true 9 1
DB10M Channel B Differential output data D10 and D11 multiplexed, complement 8 1
DB12P Channel B Differential output data D12 and D13 multiplexed, true 11 1
DB12M Channel B Differential output data D12 and D13 multiplexed, complement 10 1
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