Datasheet

ADS62P45, ADS62P44
ADS62P43, ADS62P42
www.ti.com SLAS561C –JULY 2007– REVISED FEBRUARY 2012
Pin Assignments (CMOS INTERFACE)
NUMBER OF
PIN NAME DESCRIPTION PIN NUMBER
PINS
AVDD Analog power supply 16, 33, 34 3
AGND Analog ground 17, 18, 21, 22, 24, 9
27, 28, 31, 32
CLKP, CLKM Differential input clock 25, 26 2
INM_A, INP_A Differential input signal-Channel A. When not used, the analog input pins 29, 30 2
(INM_A, INP_A) MUST be tied to VCM and CANNOT be floated.
INM_B, INP_B Differential input signal-Channel B. When not used, the analog input pins 19, 20 2
(INM_B, INP_B) MUST be tied to VCM and CANNOT be floated.
VCM Internal reference mode – Common-mode voltage output. 23 1
External reference mode – Reference input. The voltage forced on this pin sets
the ADC internal references.
RESET Serial interface RESET input. 12 1
In serial interface mode, the user must initialize internal registers through
hardware RESET by applying a high-going pulse on this pin or by using
software reset (refer to Serial Interface section).
In parallel interface mode, the user has to tie RESET pin permanently high.
(SCLK, SDATA and SEN are used as parallel pin controls in this mode) The pin
has an internal 100-kΩ pull-down resistor.
SCLK This pin functions as serial interface clock input when RESET is low. 13 1
It functions as analog control pin when RESET is tied high and controls coarse
gain and internal/external reference selection. See Table 4 for details.
The pin has an internal pull-down resistor to ground.
SDATA This pin functions as serial interface data input when RESET is low. The pin has 14 1
an internal pull-down resistor to ground.
SEN This pin functions as serial interface enable input when RESET is low. 15 1
It functions as analog control pin when RESET is tied high and controls the
output interface (LVDS/CMOS) and data format selection. See Table 5 for
details.
The pin has an internal pull-up resistor to AVDD.
CTRL1 These are digital logic input pins. Together they control various power down and 35 1
multiplexed mode. see Table 6 for details
CTRL2 36 1
CTRL3 37 1
DA0 to DA13 Channel A 14-bit data outputs, CMOS 40-47, 50-55 14
DB0 to DB13 Channel B 14-bit data outputs, CMOS 60-63, 2-11 14
CLKOUT CMOS Output clock 57 1
DRVDD Digital supply 1, 38, 48, 58 4
DRGND Digital ground 39, 49, 59, 64 and 4
PAD
PAD Digital ground. Solder the bottom pad to the digital ground on the board using – 1
multiple vias for good electrical and thermal performance.
SDOUT It functions as serial data readout pin ONLY when <SERIAL READOUT> = 1. 56 1
When <SERIAL READOUT> = 0, SDOUT pin is forced low or high by the
device (and not put in high-impedance state). If serial readout is not used,
SDOUT pin has to be floated and should not be connected on the board.
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