Datasheet

ADS62P45, ADS62P44
ADS62P43, ADS62P42
SLAS561C –JULY 2007– REVISED FEBRUARY 2012 www.ti.com
Table 17.
A7–A0
D7 D6 D5 D4 D3 D2 D1 D0
(hex)
<OFFSET TC> <GAIN CORRECTION>
1A <LOW LATENCY>
Offset correction time constant 0 to 0.5 dB, steps of 0.05 dB
D2–D0 <GAIN CORRECTION> Enables fine gain correction in steps of 0.05 dB (same correction applies to both channels)
0000 0 dB gain, default after reset
0001 +0.5 dB gain
0010 +0.10 dB gain
0011 +0.15 dB gain
0100 +0.20 dB gain
0101 +0.25 dB gain
0110 +0.30 dB gain
0111 +0.35 dB gain
1000 +0.40 dB gain
1001 +0.45 dB gain
1010 +0.5 dB gain
D6-D4 <OFFSET TC> Time constant of offset correction in number of clock cycles (seconds, for sampling frequency = 125
MSPS)
000 2
27
(1.1 s)
001 2
26
(0.55 s)
010 2
25
(0.27 s)
011 2
24
(0.13 s)
100 2
28
(2.15 s)
101 2
29
(4.3 s)
110 2
27
(1.1 s)
111 2
27
(1.1 s)
D7 <LOW LATENCY>
0 Default latency, 14 clock cycles
1 Low latency enabled, 10 clock cycles – Digital Processing Block is bypassed.
Table 18.
A7–A0
D7 D6 D5 D4 D3 D2 D1 D0
(hex)
<FILTER COEFF
<OFFSET Enable>
SELECT> <FILTER Enable> <DECIMATION RATE>
<ODD TAP
1B Offset correction 0
Enable>
In-built or custom Enable digital filtering Decimate by 2,4,8
enable
coefficients
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Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42